[[!tag standards]]

# Vector Pack/Unpack operations

In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack and unpack operations. Additional pixel pack/unpack instructions
also exist.

In SVP64, Pack and Unpack are achieved *in the abstract* for application on *all*
Vectorizeable instructions.

* See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
* <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-June/004911.html>

The effect of Pack and unpack could be covered by [[sv/remap]] by using Matrix 2D layouts on either source or destination but is quite expensive to do so.  Additionally,
with pressure on the Scalar 32-bit opcode space it is more appropriate to
compromise by adding required capability in SVP64 as a high priority
(part of the Management Instructions).  [[sv/mv.swizzle]] is sufficiently
unusual to justify a base Scalar 32-bit instruction but pack/unpack is not.
What, ultimately, was decided, was to make Pack/Unpack part of the
`SVSTATE` [[sv/spr]].

# SVSTATE Pack/unpack Mode bits

Described in [[svp64/appendix]] the Pack/Unpack Modes allow selective
Transposition of Sub-vector elements, on both source and destination.
[[sv/mv.swizzle]] is unique in that the Subvector length may be different
for source and destination.