# External RFC ls001.po9 Allocation of new 64-bit Power ISA Encodings

**URLs**:

* <https://git.openpower.foundation/isa/PowerISA/issues/64>

**Severity**: Major

**Status**: New

**Date**: 29 Apr 2023. v1

**Target**: v3.2B

**Source**: v3.0B

**Books and Section affected**:

```
    New Section: 1.6.5
    New Definitions: 1.3.1
```

**Summary**

```
    Introduces a new 64-bit encoding similar to EXT1xx in PO1, in which
    32 new Primary Opcodes are introduced (EXT2xx), several RESERVED spaces
    (57-bit and at least three 32-bit), and the RISC-paradigm Prefixing
    concepts are introduced: SVP64 and SVP64Single.
```

**Submitter**: Luke Leighton (Libre-SOC)

**Requester**: Libre-SOC

**Impact on processor**:

```
    Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
    Encoding concept, introduction of new 64-bit Encodings specifically
    designed to be easily identifiable extremely early in Multi-Issue
    systems
```

**Impact on software**:

```
    Requires support for new instructions in assembler, debuggers, and related tools.
```

**Keywords**:

```
    64-bit Encoding
```

**Motivation**

Power ISA Encoding is a finite precious resource that is under pressure.
New Primary Opcode areas are needed (beyond those already strictly defined
as EXT1xx).  New Primary Opcode areas EXT232-263 allows for immediate growth,
allowing Power ISA to catch up 12-15 years on Intel and ARM.  Also the
Simple-V RISC-paradigm "Loop" subsystem based on x86 REP and Zilog Z80
CPIR and LDIR may be cleanly and smoothly introduced.  Also several new
areas are RESERVED which allows significant future expansion.

**Changes**

Add the following entries to:

* Section 1.3.1 Book I
* Section 1.6.5 Book I

[[!tag opf_rfc]]

--------

\newpage{}

[[!inline pages="openpower/sv/po9_encoding" raw=yes ]]