# RFC ls008 SVP64 Management instructions

**URLs**:

* <https://libre-soc.org/openpower/sv/>
* <https://libre-soc.org/openpower/sv/rfc/ls008/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
* <https://git.openpower.foundation/isa/PowerISA/issues/123>

**Severity**: Major

**Status**: New

**Date**: 24 Mar 2023

**Target**: v3.2B

**Source**: v3.0B

**Books and Section affected**:

```
    Book I, new Scalar Chapter.  (Or, new Book on "Zero-Overhead Loop Subsystem")
    Appendix E Power ISA sorted by opcode
    Appendix F Power ISA sorted by version
    Appendix G Power ISA sorted by Compliancy Subset
    Appendix H Power ISA sorted by mnemonic
```

**Summary**

```
    setvl    - Cray-style "Set Vector Length" instruction
    svstep   - Vertical-First Mode explicit Step and Status
```

**Submitter**: Luke Leighton (Libre-SOC)

**Requester**: Libre-SOC

**Impact on processor**:

```
    Addition of two new "Zero-Overhead-Loop-Control" DSP-style Vector-style
    Management Instructions which can be implemented extremely efficiently
    and effectively by inserting an additional phase between Decode and Issue.
    More complex designs are NOT adversely impacted and in fact greatly benefit
```

**Impact on software**:

```
    Requires support for new instructions in assembler, debuggers,
    and related tools.
```

**Keywords**:

```
    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
    Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
    Digital Signal Processing (DSP)
```

**Motivation**

Power ISA is synonymous with Supercomputing and the early Supercomputers
(ETA-10, ILLIAC-IV, CDC200, Cray) had Vectorisation. It is therefore anomalous
that Power ISA does not have Scalable Vectors.  This presents the opportunity to
modernise Power ISA keeping it at the top of Supercomputing.

**Notes and Observations**:

1. SVP64 is very much designed for ultra-light-weight Embedded use-cases all the
  way up to moving the bar of Supercomputing orders of magnitude above its present
  perception, whilst retaining at all times Sequential Programming Execution.
2. This proposal is the **base** for further Extensions.  These include
  extending SVP64 onto the Scalar VSX instructions (with a **LONG TERM** view in 10+ years
  to deprecating the PackedSIMD aspects of VSX), to be discussed at a later
  time, the potential for extending VSX registers to 128 or beyond, and Arithmetic
  operations to a runtime-selectable choice of 128-bit, 256-bit, 512-bit or 1024-bit.
3. Massive reductions in instruction count of between 2x and 20x have been demonstrated
  with SVP64, which is far beyond anything ever achieved by any *general-purpose*
  ISA Extension added to any ISA in the history of Computing.

**Changes**

Add the following entries to:

* Section 1.3.2 Notation
* the Appendices of Book I
* Instructions of Book I as a new Section
* SVL-Form of Book I Section 1.6.1.6 and 1.6.2

----------------

\newpage{}

# Notation, Section 1.3.2

When destination register operands (`RT, RS`) are prefixed by a single
underscore (`_RT, _RS`) the variable also contains the contents of the
instruction field.
This avoids confusion in pseudocode when a destination register is
assigned (`RT <- x`) but earlier it was the operand bits that were
checked (`if RT = 0`)

----------------

\newpage{}

[[!inline pages="openpower/sv/svstep" raw=yes ]]
[[!inline pages="openpower/sv/setvl" raw=yes ]]
[[!inline pages="openpower/sv/sprs" raw=yes ]]

----------------

\newpage{}

# SVL-Form

Add the following to Book I, 1.6.1, SVL-Form

```
    |0     |6    |11    |16   |23 |24 |25 |26    |31 |
    | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
    | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
```

* Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
* Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
* Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
* Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2

Add the following to Book I, 1.6.2

```
    ms (23)
        Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
        is to be set
        Formats: SVL
    vf (25)
        Field used in Simple-V to specify whether "Vertical" Mode is set
        (vfirst in the SVSTATE SPR)
        Formats: SVL
    vs (24)
        Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
        Formats: SVL
    SVi (16:22)
         Simple-V immediate field used by setvl for setting VL or MVL
         (vl, maxvl in the SVSTATE SPR)
         and used as a "Mode of Operation" selector in svstep
         Formats: SVL
```

# Appendices

    Appendix E Power ISA sorted by opcode
    Appendix F Power ISA sorted by version
    Appendix G Power ISA sorted by Compliancy Subset
    Appendix H Power ISA sorted by mnemonic

| Form | Book | Page | Version | mnemonic | Description |
|------|------|------|---------|----------|-------------|
| SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status reporting |
| SVL  | I    | #    | 3.0B    | setvl    | Cray-like establishment of Looping (Vector) context |

[[!tag opf_rfc]]