# RFC ls010 Simple-V Zero-Overhead Loop Prefix Subsystem

* Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
  Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
* <https://www.sigarch.org/simd-instructions-considered-harmful/>
* <https://libre-soc.org/openpower/sv/>
* <https://libre-soc.org/openpower/sv/rfc/ls010/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1056>
* <https://git.openpower.foundation/isa/PowerISA/issues/64>
* <https://git.openpower.foundation/isa/PowerISA/issues/122>
* <https://libre-soc.org/openpower/sv/ls010/trial_addi/>
* <https://libre-soc.org/openpower/sv/ls010/hypothetical_addi/>

**Severity**: Major

**Status**: New

**Date**: 04 Apr 2023. v2 TODO

**Target**: v3.2B

**Source**: v3.1B

**Books and Section affected**:

```
    New Book: new Zero-Overhead-Loop
    New Appendix, Zero-Overhead-Loop
```

**Summary**

```
    Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
    in a RISC-paradigm fashion. Total instructions six 5-bit XO, plus Prefix format (PO9).
```

**Submitter**: Luke Leighton (Libre-SOC)

**Requester**: Libre-SOC

**Impact on processor**:

```
    Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
    subsystem that in simple low-end (Embedded) systems may be minimalistically
    and easily be implemented by inserting a new fully-independent Pipeline Stage
    in between Decode and Issue, with very little disruption, and in higher
    performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
    to significantly boost performance.
```

**Impact on software**:

```
    Requires support for new instructions in assembler, debuggers, and related tools.
    Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
```

**Keywords**:

```
    Cray Supercomputing, Vectorization, Zero-Overhead-Loop-Control (ZOLC),
    True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
    Digital Signal Processing (DSP), High-level Assembler
```

**Motivation**

Just at the time when customers are asking for higher performance,
the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
Harmful" article, is getting out of control and damaging the reputation
of mainstream general-purpose ISAs that offer it.  A solution from
50 years ago exists in the form of Cray-Style True-Scalable Vectors.
However the usual way that True-Scalable Vector ISAs are done *also*
adds more instructions and complexifies the ISA.  Simple-V takes a step
back to a simpler era in computing from half a century ago: the Zilog
Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
them forward to Modern-day Computing.  The result is a huge reduction in
programming complexity, and a strong base to project the Power ISA back
to the world's most powerful Supercomputing ISA for at least the next two
decades.

**Notes and Observations**:

Related RFCs are [[ls008]] for the two Management instructions `setvl`
and `svstep`, and [[ls009]] for the REMAP Subsystem. Also [[ls001]] is
a Dependency as it introduces Primary Opcode 9 64-bit encoding. An
additional RFC [[ls005.xlen]] introduced XLEN on which SVP64 is also critically
dependent, for Element-width Overrides.

**Changes**

Add the following entries to:

* A new "Vector Looping" Book
* New Vector-Looping Chapters
* New Vector-Looping Appendices

[[!tag opf_rfc]]

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