# LD/ST-Update-PostIncrement

TODO (key stub notes below)

* <https://bugs.libre-soc.org/show_bug.cgi?id=1048>

The following instructions are proposed to be added in EXT2xx,
duplicating LD/ST-Update functionality but moving the update
of RA to *after* the Memory operation.  These types of
instructions are already present in x86 (sort-of).

* x86 chose that store should be pre-indexed and load should be post-indexed
* Power ISA chose everything to be pre-indexed
* Motorola 68000 (decades old) has pre- and post- indexed

<https://tack.sourceforge.net/olddocs/m68020.html#2.2.2.%20Extra%20MC68020%20addressing%20modes>

<https://azeria-labs.com/memory-instructions-load-and-store-part-4/>

The LD/ST-Immediate-Post-Increment instructions are all Primary
Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
are all effectively 9-bit XO and consequently may easily
fit into one single Primary Opcode.  EXT2xx is recommended.

One alternative idea is that bit 31 could be allocated (retrospectively)
to Post-Increment.  Although it may be too late for Scalar Power ISA
it **may** be possible to consider for SVP64Single and/or SVP64-Vector,
but this risks creating a non-Orthogonal ISA.



```
# LD/ST-Postincrement
lbzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lbzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
lhzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lhzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
lhaup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lhaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
lwzup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lwzupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
lwaupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
ldup,     ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
ldupx,    ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
stbup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
stbupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
sthup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
sthupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W

# FP LD/ST-Postincrement
lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
lfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
lsdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W
stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W

# LD/ST-Shifted-Postincrement
lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W

# FP LD/ST-Shifted-Postincrement
lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
lfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W

```

# Example

** Load Byte and Zero with Post-Update**

D-Form

* lbzup RT,D(RA)

Pseudo-code:

```
    EA <- (RA)
    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
    RA <- (RA) + EXTS(D)
```

Special Registers Altered:

```
    None
```

where the same pseudocode for `lbzu` is:

```
    EA <- (RA) + EXTS(D)
    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
    RA <- EA
```

[[!tag opf_rfc]]