# OpenPOWER SV setvl/setvli

See links:

* <http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001366.html>
* <https://bugs.libre-soc.org/show_bug.cgi?id=535>
* <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>

# Format

| 0..5 |6..10|11..15|16.20|21.22.23.24..25|26.....30|31|  name   |
|------|-----|------|-----|---------------|---------|--|---------|
| 19   | RT  | RA   |     | XO[0:4]       | XO[5:9] |Rc| XL-Form |
| 19   | RT  | RA   |imm  | imm //  vs ms | NNNNNN  |Rc| setvl/i |

# Pseudocode

    // instruction fields:
    rd = get_rt_field();         // bits 6..10
    ra = get_ra_field();         // bits 11..15
    vlimmed = get_immed_field(); // bits 16..22
    vs = get_vs_field();         // bit 24
    ms = get_ms_field();         // bit 25
    Rc = get_Rc_field();         // bit 31

    // set VL (or not).
    // 3 options: from SPR, from immed, from ra
    if vs {
       if ra == 0 {
           VL = SPR[SV_VL]
       } else {
           VL = vlimmed
       }
    } elif ra != 0 {
       VL = GPR[ra]
    }

    // set MVL (or not).
    // 2 options: from SPR, from immed
    if ms {
       MVL = vlimmed
    } else {
       MVL = SPR[SV_MVL]
    }

    // calculate (limit) VL
    VL = min(VL, MVL)

    // store VL, MVL
    SPR[SV_VL] = VL
    SPR[SV_MVL] = MVL

    // write rd
    if rt != 0 {
        // rt is not zero
        regs[rt] = VL;
    }
    // write CR?
    if Rc {
        // update CR from VL (not rt)
        CR0 = ....
    }