# Rewrite of SVP64 for OpenPower ISA v3.1

* [[svp64/discussion]]


The plan is to create an encoding for SVP64, then to create an encoding for
SVP48, then to reorganize them both to improve field overlap, reducing the
amount of decoder hardware necessary.

All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB and
counting up as you move to the LSB end). All bit ranges are inclusive (so
`4:6` means bits 4, 5, and 6).

64-bit instructions are split into two 32-bit words, the prefix and the suffix. The prefix always comes before the suffix in PC order.

## Remapped Encoding (`RM[0:23]`)

To allow relatively easy remapping of which portions of the Prefix Opcode Map
are used for SVP64 without needing to rewrite a large portion of the SVP64
spec, a mapping is defined from the OpenPower v3.1 prefix bits to a new 24-bit
Remapped Encoding denoted `RM[0]` at the MSB to `RM[23]` at the LSB.

The mapping from the OpenPower v3.1 prefix bits to the Remapped Encoding is
defined in the Prefix Fields section.

## Remapped Encoding Fields

| Remapped Encoding Field Name | Field bits | Description    |
|------------------------------|------------|----------------|
| MASK                         | `0:3`      | Execution Mask |
| TBD                          | `4:23`     | TBD            |

## MASK Encoding

TODO: split out (remove) bit 3 as separate so that twin predication can use the same encoding, and split the table into 2 halves. The bit currently 3 becomes a separate (standalone) field (see [discussion]) that selects *both* src and dest predication as CR based or both as INT based.  This saves one bit and makes things less complex to implement in hardware.

Integer based predication.  Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest)

| Value | Mnemonic          | Description                                            |
|-------|-------------------|--------------------------------------------------------|
| 0000  | -                 | Reserved (causes an illegal instruction trap)          |
| 0001  | ALWAYS (implicit) | Operation is not masked  see [[discussion]]                              |
| 0010  | R3                | Element `i` is enabled if `R3 & (1 << i)` is non-zero  |
| 0011  | ~R3               | Element `i` is enabled if `R3 & (1 << i)` is zero      |
| 0100  | R10               | Element `i` is enabled if `R10 & (1 << i)` is non-zero |
| 0101  | ~R10              | Element `i` is enabled if `R10 & (1 << i)` is zero     |
| 0110  | R30               | Element `i` is enabled if `R30 & (1 << i)` is non-zero |
| 0111  | ~R30              | Element `i` is enabled if `R30 & (1 << i)` is zero     |

CR based predication.  TODO: select alternate CR for twin predication? see [[discussion]]  Overlap of the two CR based predicates must be taken into account, so the starting point for one of them must be suitably high, or accept that for twin predication VL must not exceed the range where overlap will occur, *or* that they use the same starting point but select different *bits* of the same CRs

| Value | Mnemonic          | Description                                            |
|-------|-------------------|--------------------------------------------------------|
| 1000  | lt                | Element `i` is enabled if `CR[6+i].LT` is set          |
| 1001  | nl/ge             | Element `i` is enabled if `CR[6+i].LT` is clear        |
| 1010  | gt                | Element `i` is enabled if `CR[6+i].GT` is set          |
| 1011  | ng/le             | Element `i` is enabled if `CR[6+i].GT` is clear        |
| 1100  | eq                | Element `i` is enabled if `CR[6+i].EQ` is set          |
| 1101  | ne                | Element `i` is enabled if `CR[6+i].EQ` is clear        |
| 1110  | so/un             | Element `i` is enabled if `CR[6+i].FU` is set          |
| 1111  | ns/nu             | Element `i` is enabled if `CR[6+i].FU` is clear        |

## Prefix Opcode Map (64-bit instruction encoding) (prefix bits 6:11)

(shows both PowerISA v3.1 instructions as well as new SVP instructions; empty spaces are yet-to-be-allocated Illegal Instructions)

| bits 6:11 | ---000   | ---001     | ---010   | ---011   | ---100   | ---101   | ---110   | ---111   |
|-----------|----------|------------|----------|----------|----------|----------|----------|----------|
| 000---    | 8LS-form | 8LS-form   | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form | 8LS-form |
| 001---    |          |            |          |          |          |          |          |          |
| 010---    | 8RR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
| 011---    |          |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
| 100---    | MLS-form | MLS-form   | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form | MLS-form |
| 101---    |          |            |          |          |          |          |          |          |
| 110---    | MRR-form |            |          |          | SVP64    | SVP64    | SVP64    | SVP64    |
| 111---    |          | MMIRR-form |          |          | SVP64    | SVP64    | SVP64    | SVP64    |

## Prefix Fields

| Prefix Field Name   | Field bits | Constant Value | Description                                |
|---------------------|------------|----------------|--------------------------------------------|
| PO (Primary Opcode) | `0:5`      | `1`            | Indicates this is a 64-bit instruction     |
| `RM[0]`             | `6`        |                | Bit 0 of the Remapped Encoding             |
| SVP64_7             | `7`        | `1`            | Indicates this is a SVP64 instruction      |
| `RM[1]`             | `8`        |                | Bit 1 of the Remapped Encoding             |
| SVP64_9             | `9`        | `1`            | Indicates this is a SVP64 instruction      |
| `RM[2:23]`          | `10:31`    |                | Bits 2 through 23 of the Remapped Encoding |

# Register Naming

SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.

## Integer Registers

setvli ..., VL=7
add r20, r25, r30, elwidth=64, subvl=1

where r20, r25, and r30 are standard OpenPower register names.
Those names correspond to SVR20_00, SVR25_00, and SVR30_00.

pseudocode:
const STD_TO_SV_SHIFT = 2; // gets bigger as reg files expand to 256, 512,
... registers

VL=7 // setvli (omitting maxvl here)

for(i=0;i<VL;i++) {
    regs[(20 << STD_TO_SV_SHIFT) + i] = regs[(25 << STD_TO_SV_SHIFT) + i]
        + regs[(30 << STD_TO_SV_SHIFT) + i];
}

Standard PowerISA Integer registers are aliased to some of the SV integer registers:

| Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register |
|----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|----------------------|-------------------------|
| R0                   | SVR0_00                 | R8                   | SVR8_00                 | R16                  | SVR16_00                | R24                  | SVR24_00                |
|                      | SVR0_01                 |                      | SVR8_01                 |                      | SVR16_01                |                      | SVR24_01                |
|                      | SVR0_10                 |                      | SVR8_10                 |                      | SVR16_10                |                      | SVR24_10                |
|                      | SVR0_11                 |                      | SVR8_11                 |                      | SVR16_11                |                      | SVR24_11                |
| R1                   | SVR1_00                 | R9                   | SVR9_00                 | R17                  | SVR17_00                | R25                  | SVR25_00                |
|                      | SVR1_01                 |                      | SVR9_01                 |                      | SVR17_01                |                      | SVR25_01                |
|                      | SVR1_10                 |                      | SVR9_10                 |                      | SVR17_10                |                      | SVR25_10                |
|                      | SVR1_11                 |                      | SVR9_11                 |                      | SVR17_11                |                      | SVR25_11                |
| R2                   | SVR2_00                 | R10                  | SVR10_00                | R18                  | SVR18_00                | R26                  | SVR26_00                |
|                      | SVR2_01                 |                      | SVR10_01                |                      | SVR18_01                |                      | SVR26_01                |
|                      | SVR2_10                 |                      | SVR10_10                |                      | SVR18_10                |                      | SVR26_10                |
|                      | SVR2_11                 |                      | SVR10_11                |                      | SVR18_11                |                      | SVR26_11                |
| R3                   | SVR3_00                 | R11                  | SVR11_00                | R19                  | SVR19_00                | R27                  | SVR27_00                |
|                      | SVR3_01                 |                      | SVR11_01                |                      | SVR19_01                |                      | SVR27_01                |
|                      | SVR3_10                 |                      | SVR11_10                |                      | SVR19_10                |                      | SVR27_10                |
|                      | SVR3_11                 |                      | SVR11_11                |                      | SVR19_11                |                      | SVR27_11                |
| R4                   | SVR4_00                 | R12                  | SVR12_00                | R20                  | SVR20_00                | R28                  | SVR28_00                |
|                      | SVR4_01                 |                      | SVR12_01                |                      | SVR20_01                |                      | SVR28_01                |
|                      | SVR4_10                 |                      | SVR12_10                |                      | SVR20_10                |                      | SVR28_10                |
|                      | SVR4_11                 |                      | SVR12_11                |                      | SVR20_11                |                      | SVR28_11                |
| R5                   | SVR5_00                 | R13                  | SVR13_00                | R21                  | SVR21_00                | R29                  | SVR29_00                |
|                      | SVR5_01                 |                      | SVR13_01                |                      | SVR21_01                |                      | SVR29_01                |
|                      | SVR5_10                 |                      | SVR13_10                |                      | SVR21_10                |                      | SVR29_10                |
|                      | SVR5_11                 |                      | SVR13_11                |                      | SVR21_11                |                      | SVR29_11                |
| R6                   | SVR6_00                 | R14                  | SVR14_00                | R22                  | SVR22_00                | R30                  | SVR30_00                |
|                      | SVR6_01                 |                      | SVR14_01                |                      | SVR22_01                |                      | SVR30_01                |
|                      | SVR6_10                 |                      | SVR14_10                |                      | SVR22_10                |                      | SVR30_10                |
|                      | SVR6_11                 |                      | SVR14_11                |                      | SVR22_11                |                      | SVR30_11                |
| R7                   | SVR7_00                 | R15                  | SVR15_00                | R23                  | SVR23_00                | R31                  | SVR31_00                |
|                      | SVR7_01                 |                      | SVR15_01                |                      | SVR23_01                |                      | SVR31_01                |
|                      | SVR7_10                 |                      | SVR15_10                |                      | SVR23_10                |                      | SVR31_10                |
|                      | SVR7_11                 |                      | SVR15_11                |                      | SVR23_11                |                      | SVR31_11                |

## Floating-Point Registers

Standard PowerISA floating-point and VSX registers are aliased to some of the SV floating-point registers:

| FP<br/>Register | VSX Register          | SV FP<br/>Register | FP<br/>Register | VSX Register          | SV FP<br/>Register |
|-----------------|-----------------------|--------------------|-----------------|-----------------------|--------------------|
| FPR\[0\]        | VSR\[0\]\.dword\[0\]  | SVFR0\_00          | FPR\[16\]       | VSR\[16\]\.dword\[0\] | SVFR16\_00         |
|                 | VSR\[0\]\.dword\[1\]  | SVFR0\_01          |                 | VSR\[16\]\.dword\[1\] | SVFR16\_01         |
|                 | VSR\[32\]\.dword\[0\] | SVFR0\_10          |                 | VSR\[48\]\.dword\[0\] | SVFR16\_10         |
|                 | VSR\[32\]\.dword\[1\] | SVFR0\_11          |                 | VSR\[48\]\.dword\[1\] | SVFR16\_11         |
| FPR\[1\]        | VSR\[1\]\.dword\[0\]  | SVFR1\_00          | FPR\[17\]       | VSR\[17\]\.dword\[0\] | SVFR17\_00         |
|                 | VSR\[1\]\.dword\[1\]  | SVFR1\_01          |                 | VSR\[17\]\.dword\[1\] | SVFR17\_01         |
|                 | VSR\[33\]\.dword\[0\] | SVFR1\_10          |                 | VSR\[49\]\.dword\[0\] | SVFR17\_10         |
|                 | VSR\[33\]\.dword\[1\] | SVFR1\_11          |                 | VSR\[49\]\.dword\[1\] | SVFR17\_11         |
| FPR\[2\]        | VSR\[2\]\.dword\[0\]  | SVFR2\_00          | FPR\[18\]       | VSR\[18\]\.dword\[0\] | SVFR18\_00         |
|                 | VSR\[2\]\.dword\[1\]  | SVFR2\_01          |                 | VSR\[18\]\.dword\[1\] | SVFR18\_01         |
|                 | VSR\[34\]\.dword\[0\] | SVFR2\_10          |                 | VSR\[50\]\.dword\[0\] | SVFR18\_10         |
|                 | VSR\[34\]\.dword\[1\] | SVFR2\_11          |                 | VSR\[50\]\.dword\[1\] | SVFR18\_11         |
| FPR\[3\]        | VSR\[3\]\.dword\[0\]  | SVFR3\_00          | FPR\[19\]       | VSR\[19\]\.dword\[0\] | SVFR19\_00         |
|                 | VSR\[3\]\.dword\[1\]  | SVFR3\_01          |                 | VSR\[19\]\.dword\[1\] | SVFR19\_01         |
|                 | VSR\[35\]\.dword\[0\] | SVFR3\_10          |                 | VSR\[51\]\.dword\[0\] | SVFR19\_10         |
|                 | VSR\[35\]\.dword\[1\] | SVFR3\_11          |                 | VSR\[51\]\.dword\[1\] | SVFR19\_11         |
| FPR\[4\]        | VSR\[4\]\.dword\[0\]  | SVFR4\_00          | FPR\[20\]       | VSR\[20\]\.dword\[0\] | SVFR20\_00         |
|                 | VSR\[4\]\.dword\[1\]  | SVFR4\_01          |                 | VSR\[20\]\.dword\[1\] | SVFR20\_01         |
|                 | VSR\[36\]\.dword\[0\] | SVFR4\_10          |                 | VSR\[52\]\.dword\[0\] | SVFR20\_10         |
|                 | VSR\[36\]\.dword\[1\] | SVFR4\_11          |                 | VSR\[52\]\.dword\[1\] | SVFR20\_11         |
| FPR\[5\]        | VSR\[5\]\.dword\[0\]  | SVFR5\_00          | FPR\[21\]       | VSR\[21\]\.dword\[0\] | SVFR21\_00         |
|                 | VSR\[5\]\.dword\[1\]  | SVFR5\_01          |                 | VSR\[21\]\.dword\[1\] | SVFR21\_01         |
|                 | VSR\[37\]\.dword\[0\] | SVFR5\_10          |                 | VSR\[53\]\.dword\[0\] | SVFR21\_10         |
|                 | VSR\[37\]\.dword\[1\] | SVFR5\_11          |                 | VSR\[53\]\.dword\[1\] | SVFR21\_11         |
| FPR\[6\]        | VSR\[6\]\.dword\[0\]  | SVFR6\_00          | FPR\[22\]       | VSR\[22\]\.dword\[0\] | SVFR22\_00         |
|                 | VSR\[6\]\.dword\[1\]  | SVFR6\_01          |                 | VSR\[22\]\.dword\[1\] | SVFR22\_01         |
|                 | VSR\[38\]\.dword\[0\] | SVFR6\_10          |                 | VSR\[54\]\.dword\[0\] | SVFR22\_10         |
|                 | VSR\[38\]\.dword\[1\] | SVFR6\_11          |                 | VSR\[54\]\.dword\[1\] | SVFR22\_11         |
| FPR\[7\]        | VSR\[7\]\.dword\[0\]  | SVFR7\_00          | FPR\[23\]       | VSR\[23\]\.dword\[0\] | SVFR23\_00         |
|                 | VSR\[7\]\.dword\[1\]  | SVFR7\_01          |                 | VSR\[23\]\.dword\[1\] | SVFR23\_01         |
|                 | VSR\[39\]\.dword\[0\] | SVFR7\_10          |                 | VSR\[55\]\.dword\[0\] | SVFR23\_10         |
|                 | VSR\[39\]\.dword\[1\] | SVFR7\_11          |                 | VSR\[55\]\.dword\[1\] | SVFR23\_11         |
| FPR\[8\]        | VSR\[8\]\.dword\[0\]  | SVFR8\_00          | FPR\[24\]       | VSR\[24\]\.dword\[0\] | SVFR24\_00         |
|                 | VSR\[8\]\.dword\[1\]  | SVFR8\_01          |                 | VSR\[24\]\.dword\[1\] | SVFR24\_01         |
|                 | VSR\[40\]\.dword\[0\] | SVFR8\_10          |                 | VSR\[56\]\.dword\[0\] | SVFR24\_10         |
|                 | VSR\[40\]\.dword\[1\] | SVFR8\_11          |                 | VSR\[56\]\.dword\[1\] | SVFR24\_11         |
| FPR\[9\]        | VSR\[9\]\.dword\[0\]  | SVFR9\_00          | FPR\[25\]       | VSR\[25\]\.dword\[0\] | SVFR25\_00         |
|                 | VSR\[9\]\.dword\[1\]  | SVFR9\_01          |                 | VSR\[25\]\.dword\[1\] | SVFR25\_01         |
|                 | VSR\[41\]\.dword\[0\] | SVFR9\_10          |                 | VSR\[57\]\.dword\[0\] | SVFR25\_10         |
|                 | VSR\[41\]\.dword\[1\] | SVFR9\_11          |                 | VSR\[57\]\.dword\[1\] | SVFR25\_11         |
| FPR\[10\]       | VSR\[10\]\.dword\[0\] | SVFR10\_00         | FPR\[26\]       | VSR\[26\]\.dword\[0\] | SVFR26\_00         |
|                 | VSR\[10\]\.dword\[1\] | SVFR10\_01         |                 | VSR\[26\]\.dword\[1\] | SVFR26\_01         |
|                 | VSR\[42\]\.dword\[0\] | SVFR10\_10         |                 | VSR\[58\]\.dword\[0\] | SVFR26\_10         |
|                 | VSR\[42\]\.dword\[1\] | SVFR10\_11         |                 | VSR\[58\]\.dword\[1\] | SVFR26\_11         |
| FPR\[11\]       | VSR\[11\]\.dword\[0\] | SVFR11\_00         | FPR\[27\]       | VSR\[27\]\.dword\[0\] | SVFR27\_00         |
|                 | VSR\[11\]\.dword\[1\] | SVFR11\_01         |                 | VSR\[27\]\.dword\[1\] | SVFR27\_01         |
|                 | VSR\[43\]\.dword\[0\] | SVFR11\_10         |                 | VSR\[59\]\.dword\[0\] | SVFR27\_10         |
|                 | VSR\[43\]\.dword\[1\] | SVFR11\_11         |                 | VSR\[59\]\.dword\[1\] | SVFR27\_11         |
| FPR\[12\]       | VSR\[12\]\.dword\[0\] | SVFR12\_00         | FPR\[28\]       | VSR\[28\]\.dword\[0\] | SVFR28\_00         |
|                 | VSR\[12\]\.dword\[1\] | SVFR12\_01         |                 | VSR\[28\]\.dword\[1\] | SVFR28\_01         |
|                 | VSR\[44\]\.dword\[0\] | SVFR12\_10         |                 | VSR\[60\]\.dword\[0\] | SVFR28\_10         |
|                 | VSR\[44\]\.dword\[1\] | SVFR12\_11         |                 | VSR\[60\]\.dword\[1\] | SVFR28\_11         |
| FPR\[13\]       | VSR\[13\]\.dword\[0\] | SVFR13\_00         | FPR\[29\]       | VSR\[29\]\.dword\[0\] | SVFR29\_00         |
|                 | VSR\[13\]\.dword\[1\] | SVFR13\_01         |                 | VSR\[29\]\.dword\[1\] | SVFR29\_01         |
|                 | VSR\[45\]\.dword\[0\] | SVFR13\_10         |                 | VSR\[61\]\.dword\[0\] | SVFR29\_10         |
|                 | VSR\[45\]\.dword\[1\] | SVFR13\_11         |                 | VSR\[61\]\.dword\[1\] | SVFR29\_11         |
| FPR\[14\]       | VSR\[14\]\.dword\[0\] | SVFR14\_00         | FPR\[30\]       | VSR\[30\]\.dword\[0\] | SVFR30\_00         |
|                 | VSR\[14\]\.dword\[1\] | SVFR14\_01         |                 | VSR\[30\]\.dword\[1\] | SVFR30\_01         |
|                 | VSR\[46\]\.dword\[0\] | SVFR14\_10         |                 | VSR\[62\]\.dword\[0\] | SVFR30\_10         |
|                 | VSR\[46\]\.dword\[1\] | SVFR14\_11         |                 | VSR\[62\]\.dword\[1\] | SVFR30\_11         |
| FPR\[15\]       | VSR\[15\]\.dword\[0\] | SVFR15\_00         | FPR\[31\]       | VSR\[31\]\.dword\[0\] | SVFR31\_00         |
|                 | VSR\[15\]\.dword\[1\] | SVFR15\_01         |                 | VSR\[31\]\.dword\[1\] | SVFR31\_01         |
|                 | VSR\[47\]\.dword\[0\] | SVFR15\_10         |                 | VSR\[63\]\.dword\[0\] | SVFR31\_10         |
|                 | VSR\[47\]\.dword\[1\] | SVFR15\_11         |                 | VSR\[63\]\.dword\[1\] | SVFR31\_11         |


# Operation

## CR fields as inputs/outputs of vector operations

When vectorized, the CR inputs/outputs are read/written to 4-bit CR fields
starting from CR6 and incrementing from there. If CR63 is reached, the next CR
field used wraps around to CR0, then incrementing from there.
(see [[discussion]].  an alternative scheme is described there)

CR6 was chosen to balance avoiding needing to save CR2-CR4 (which are
callee-saved) just to use SV vectors with VL <= 61 as well as having the first
few used CR fields readily accessible to standard CR instructions and branches.
Additionally, CR6 is used as the implicit result of a OpenPower ISA v3.1
standard vector instruction with Rc=1.

# Register Profiles

Instructions are broken down by Register Profiles as listed in the following auto-generated page:
[[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (mtspr, bc, dcbz, twi)

## LDST-1R-1W-imm
TBD
## LDST-1R-2W-imm
TBD
## LDST-2R-imm
TBD
## LDST-2R-1W
TBD
## LDST-2R-1W-imm
TBD
## LDST-2R-2W
TBD
## LDST-3R
TBD
## LDST-3R-CRo
TBD
## LDST-3R-1W
TBD
## CRi
non-SV
## CRio
TBD
## CR=2R1W
TBD
## 1W
non-SV
## 1W-CRi
TBD
## 1R
non-SV
## 1R-imm
non-SV
## 1R-CRo
TBD
## 1R-CRio
TBD
## 1R-1W
TBD
## 1R-1W-imm
TBD
## 1R-1W-CRo
TBD
## 1R-1W-CRo
TBD
## 1R-1W-CRio
TBD
## 2R
non-SV
## 2R-CRo
TBD
## 2R-CRio
TBD
## 2R-1W
TBD
## 2R-1W-CRo
TBD
## 2R-1W-CRo
TBD
## 2R-1W-CRi
TBD
## 2R-1W-CRio
TBD
## 3R-1W-CRio

Remapped Encoding Fields:

|  |
|--|
|  |