# Simple-V Vectorisation for the OpenPOWER ISA

Fundamental design principles:

* Simplicity of introduction and implementation on the existing OpenPOWER ISA
* Effectively a hardware for-loop, pausing PC, issuing multiple scalar operations
* Preserving the underlying scalar execution dependencies as if the for-loop had been expanded as actual scalar instructions.
* Augments ("tags") existing instructions, providing Vectorisation "context" rather than adding new ones.
* Does not modify or deviate from the underly scalar OpenPOWER ISA unless it provides significant performance or other advantage to do so in the Vector space (dropping XER.SO and OE=1 for example)

Advantages of these design principles:

* It is therefore easy to create a first (and sometimes only) implementation as literally a for-loop in hardware, simulators, and compilers.
* More complex HDL can be done by repeating existing scalar ALUs and pipelines as blocks.
* As (mostly) a high-level "context" that does not (significantly) deviate from scalar OpenPOWER ISA and, in its purest form being "a for loop around scalar instructions", it is minimally-disruptive and consequently stands a reasonable chance of broad community adoption and acceptance

Pages being developed and examples

* [[sv/predication]]
* [[sv/masked_vector_chaining]]
* [[sv/discussion]]
* [[sv/example_dep_matrices]]
* [[sv/prefix]]
* [[sv/major_opcode_allocation]]
* [[opcode_regs_deduped]]