# RV32I "RV32I Base Integer Instruction Set" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |lui | rd imm20 | u | rv32i rv64i rv128i | - | |auipc | rd oimm20 | u+o | rv32i rv64i rv128i | - | |jal | rd jimm20 | uj | rv32i rv64i rv128i | - | |jalr | rd rs1 oimm12 | i+o | rv32i rv64i rv128i | - | |beq | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |bne | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |blt | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |bge | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |bltu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |bgeu | rs1 rs2 sbimm12 | sb | rv32i rv64i rv128i | | |lb | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | | |lh | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | | |lw | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | | |lbu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | | |lhu | rd rs1 oimm12 | i+l | rv32i rv64i rv128i | | |sb | rs1 rs2 simm12 | s | rv32i rv64i rv128i | | |sh | rs1 rs2 simm12 | s | rv32i rv64i rv128i | | |sw | rs1 rs2 simm12 | s | rv32i rv64i rv128i | | |addi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |slti | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |sltiu | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |xori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |ori | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |andi | rd rs1 imm12 | i | rv32i rv64i rv128i | sv | |slli | rd rs1 shamt5 | i·sh5 | rv32i | sv | |srli | rd rs1 shamt5 | i·sh5 | rv32i | sv | |srai | rd rs1 shamt5 | i·sh5 | rv32i | sv | |add | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |sub | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |sll | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |slt | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |sltu | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |xor | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |srl | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |sra | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |or | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |and | rd rs1 rs2 | r | rv32i rv64i rv128i | sv | |fence | | r·f | rv32i rv64i rv128i | - | |fence.i | | none | rv32i rv64i rv128i | - | # RV64I "RV64I Base Integer Instruction Set (in addition to RV32I)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |lwu | rd rs1 oimm12 | i+l | rv64i rv128i | | |ld | rd rs1 oimm12 | i+l | rv64i rv128i | | |sd | rs1 rs2 simm12 | s | rv64i rv128i | | |slli | rd rs1 shamt6 | i·sh6 | rv64i | | |srli | rd rs1 shamt6 | i·sh6 | rv64i | | |srai | rd rs1 shamt6 | i·sh6 | rv64i | | |addiw | rd rs1 imm12 | i | rv64i rv128i | | |slliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | |srliw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | |sraiw | rd rs1 shamt5 | i·sh5 | rv64i rv128i | | |addw | rd rs1 rs2 | r | rv64i rv128i | | |subw | rd rs1 rs2 | r | rv64i rv128i | | |sllw | rd rs1 rs2 | r | rv64i rv128i | | |srlw | rd rs1 rs2 | r | rv64i rv128i | | |sraw | rd rs1 rs2 | r | rv64i rv128i | | # RV128I "RV128I Base Integer Instruction Set (in addition to RV64I)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |ldu | rd rs1 oimm12 | i+l | rv128i | | |lq | rd rs1 oimm12 | i+l | rv128i | | |sq | rs1 rs2 simm12 | s | rv128i | | |slli | rd rs1 shamt7 | i·sh7 | rv128i | | |srli | rd rs1 shamt7 | i·sh7 | rv128i | | |srai | rd rs1 shamt7 | i·sh7 | rv128i | | |addid | rd rs1 imm12 | i | rv128i | | |sllid | rd rs1 shamt6 | i·sh6 | rv128i | | |srlid | rd rs1 shamt6 | i·sh6 | rv128i | | |sraid | rd rs1 shamt6 | i·sh6 | rv128i | | |addd | rd rs1 rs2 | r | rv128i | | |subd | rd rs1 rs2 | r | rv128i | | |slld | rd rs1 rs2 | r | rv128i | | |srld | rd rs1 rs2 | r | rv128i | | |srad | rd rs1 rs2 | r | rv128i | | # RV32M "RV32M Standard Extension for Integer Multiply and Divide" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |mul | rd rs1 rs2 | r | rv32m rv64m rv128m | | |mulh | rd rs1 rs2 | r | rv32m rv64m rv128m | | |mulhsu | rd rs1 rs2 | r | rv32m rv64m rv128m | | |mulhu | rd rs1 rs2 | r | rv32m rv64m rv128m | | |div | rd rs1 rs2 | r | rv32m rv64m rv128m | | |divu | rd rs1 rs2 | r | rv32m rv64m rv128m | | |rem | rd rs1 rs2 | r | rv32m rv64m rv128m | | |remu | rd rs1 rs2 | r | rv32m rv64m rv128m | | # RV64M "RV64M Standard Extension for Integer Multiply and Divide (in addition to RV32M)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |mulw | rd rs1 rs2 | r | rv64m rv128m | | |divw | rd rs1 rs2 | r | rv64m rv128m | | |divuw | rd rs1 rs2 | r | rv64m rv128m | | |remw | rd rs1 rs2 | r | rv64m rv128m | | |remuw | rd rs1 rs2 | r | rv64m rv128m | | # RV128M "RV128M Standard Extension for Integer Multiply and Divide (in addition to RV64M)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |muld | rd rs1 rs2 | r | rv128m | | |divd | rd rs1 rs2 | r | rv128m | | |divud | rd rs1 rs2 | r | rv128m | | |remd | rd rs1 rs2 | r | rv128m | | |remud | rd rs1 rs2 | r | rv128m | | # RV32A "RV32A Standard Extension for Atomic Instructions" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |lr.w | rd rs1 | r·l | rv32a rv64a rv128a | | |sc.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amoswap.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amoadd.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amoxor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amoor.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amoand.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amomin.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amomax.w | rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amominu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | |amomaxu.w| rd rs1 rs2 | r·a | rv32a rv64a rv128a | | # RV64A "RV64A Standard Extension for Atomic Instructions (in addition to RV32A)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |lr.d | rd rs1 | r·l | rv64a rv128a | | |sc.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amoswap.d| rd rs1 rs2 | r·a | rv64a rv128a | | |amoadd.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amoxor.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amoor.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amoand.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amomin.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amomax.d | rd rs1 rs2 | r·a | rv64a rv128a | | |amominu.d| rd rs1 rs2 | r·a | rv64a rv128a | | |amomaxu.d| rd rs1 rs2 | r·a | rv64a rv128a | | # RV128A "RV128A Standard Extension for Atomic Instructions (in addition to RV64A)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |lr.q | rd rs1 | r·l | rv128a | | |sc.q | rd rs1 rs2 | r·a | rv128a | | |amoswap.q| rd rs1 rs2 | r·a | rv128a | | |amoadd.q | rd rs1 rs2 | r·a | rv128a | | |amoxor.q | rd rs1 rs2 | r·a | rv128a | | |amoor.q | rd rs1 rs2 | r·a | rv128a | | |amoand.q | rd rs1 rs2 | r·a | rv128a | | |amomin.q | rd rs1 rs2 | r·a | rv128a | | |amomax.q | rd rs1 rs2 | r·a | rv128a | | |amominu.q| rd rs1 rs2 | r·a | rv128a | | |amomaxu.q| rd rs1 rs2 | r·a | rv128a | | # RV32S "RV32S Standard Extension for Supervisor-level Instructions" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |ecall | | none | rv32s rv64s rv128s | | |ebreak | | none | rv32s rv64s rv128s | | |uret | | none | rv32s rv64s rv128s | | |sret | | none | rv32s rv64s rv128s | | |hret | | none | rv32s rv64s rv128s | | |mret | | none | rv32s rv64s rv128s | | |dret | | none | rv32s rv64s rv128s | | |sfence.vm | rs1 | r+sf | rv32s rv64s rv128s | | |sfence.vma| rs1 rs2 | r+sfa | rv32s rv64s rv128s | | |wfi | | none | rv32s rv64s rv128s | | |csrrw | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | |csrrs | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | |csrrc | rd rs1 csr12 | i·csr | rv32s rv64s rv128s | | |csrrwi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | |csrrsi | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | |csrrci | rd zimm csr12 | i·csr+i | rv32s rv64s rv128s | | # RV32F "RV32F Standard Extension for Single-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |flw | frd rs1 oimm12 | i+lf | rv32f rv64f rv128f | | |fsw | rs1 frs2 simm12 | s+f | rv32f rv64f rv128f | | |fmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | |fmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | |fnmsub.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | |fnmadd.s | frd frs1 frs2 frs3 rm | r4·m | rv32f rv64f rv128f | | |fadd.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | |fsub.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | |fmul.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | |fdiv.s | frd frs1 frs2 rm | r·m+3f | rv32f rv64f rv128f | | |fsgnj.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | |fsgnjn.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | |fsgnjx.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | |fmin.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | |fmax.s | frd frs1 frs2 | r+3f | rv32f rv64f rv128f | | |fsqrt.s | frd frs1 rm | r·m+ff | rv32f rv64f rv128f | | |fle.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | |flt.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | |feq.s | rd frs1 frs2 | r+rff | rv32f rv64f rv128f | | |fcvt.w.s | rd frs1 rm | r·m+rf | rv32f rv64f rv128f | | |fcvt.wu.s| rd frs1 rm | r·m+rf | rv32f rv64f rv128f | | |fcvt.s.w | frd rs1 rm | r·m+fr | rv32f rv64f rv128f | | |fcvt.s.wu| frd rs1 rm | r·m+fr | rv32f rv64f rv128f | | |fmv.x.s | rd frs1 | r+rf | rv32f rv64f rv128f | | |fclass.s | rd frs1 | r+rf | rv32f rv64f rv128f | | |fmv.s.x | frd rs1 | r+fr | rv32f rv64f rv128f | | # RV64F "RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |fcvt.l.s | rd frs1 rm | r·m+rf | rv64f rv128f | | |fcvt.lu.s| rd frs1 rm | r·m+rf | rv64f rv128f | | |fcvt.s.l | frd rs1 rm | r·m+fr | rv64f rv128f | | |fcvt.s.lu| frd rs1 rm | r·m+fr | rv64f rv128f | | # RV32D "RV32D Standard Extension for Double-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |fld | frd rs1 oimm12 | i+lf | rv32d rv64d rv128d | | |fsd | rs1 frs2 simm12 | s+f | rv32d rv64d rv128d | | |fmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | |fmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | |fnmsub.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | |fnmadd.d | frd frs1 frs2 frs3 rm | r4·m | rv32d rv64d rv128d | | |fadd.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | |fsub.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | |fmul.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | |fdiv.d | frd frs1 frs2 rm | r·m+3f | rv32d rv64d rv128d | | |fsgnj.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | |fsgnjn.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | |fsgnjx.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | |fmin.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | |fmax.d | frd frs1 frs2 | r+3f | rv32d rv64d rv128d | | |fcvt.s.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | |fcvt.d.s | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | |fsqrt.d | frd frs1 rm | r·m+ff | rv32d rv64d rv128d | | |fle.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | |flt.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | |feq.d | rd frs1 frs2 | r+rff | rv32d rv64d rv128d | | |fcvt.w.d | rd frs1 rm | r·m+rf | rv32d rv64d rv128d | | |fcvt.wu.d| rd frs1 rm | r·m+rf | rv32d rv64d rv128d | | |fcvt.d.w | frd rs1 rm | r·m+fr | rv32d rv64d rv128d | | |fcvt.d.wu| frd rs1 rm | r·m+fr | rv32d rv64d rv128d | | |fclass.d | rd frs1 | r+rf | rv32d rv64d rv128d | | # RV64D "RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |fcvt.l.d | rd frs1 rm | r·m+rf | rv64d rv128d | | |fcvt.lu.d| rd frs1 rm | r·m+rf | rv64d rv128d | | |fmv.x.d | rd frs1 | r+rf | rv64d rv128d | | |fcvt.d.l | frd rs1 rm | r·m+fr | rv64d rv128d | | |fcvt.d.lu| frd rs1 rm | r·m+fr | rv64d rv128d | | |fmv.d.x | frd rs1 | r+fr | rv64d rv128d | | # RV32Q "RV32Q Standard Extension for Quad-Precision Floating-Point" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |flq | frd rs1 oimm12 | i+lf | rv32q rv64q rv128q | | |fsq | rs1 frs2 simm12 | s+f | rv32q rv64q rv128q | | |fmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | |fmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | |fnmsub.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | |fnmadd.q | frd frs1 frs2 frs3 rm | r4·m | rv32q rv64q rv128q | | |fadd.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | |fsub.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | |fmul.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | |fdiv.q | frd frs1 frs2 rm | r·m+3f | rv32q rv64q rv128q | | |fsgnj.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | |fsgnjn.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | |fsgnjx.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | |fmin.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | |fmax.q | frd frs1 frs2 | r+3f | rv32q rv64q rv128q | | |fcvt.s.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | |fcvt.q.s | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | |fcvt.d.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | |fcvt.q.d | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | |fsqrt.q | frd frs1 rm | r·m+ff | rv32q rv64q rv128q | | |fle.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | |flt.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | |feq.q | rd frs1 frs2 | r+rff | rv32q rv64q rv128q | | |fcvt.w.q | rd frs1 rm | r·m+rf | rv32q rv64q rv128q | | |fcvt.wu.q| rd frs1 rm | r·m+rf | rv32q rv64q rv128q | | |fcvt.q.w | frd rs1 rm | r·m+fr | rv32q rv64q rv128q | | |fcvt.q.wu| frd rs1 rm | r·m+fr | rv32q rv64q rv128q | | |fclass.q | rd frs1 | r+rf | rv32q rv64q rv128q | | # RV64Q "RV64Q Standard Extension for Quad-Precision Floating-Point (in addition to RV32Q)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |fcvt.l.q | rd frs1 rm | r·m+rf | rv64q rv128q | | |fcvt.lu.q| rd frs1 rm | r·m+rf | rv64q rv128q | | |fcvt.q.l | frd rs1 rm | r·m+fr | rv64q rv128q | | |fcvt.q.lu| frd rs1 rm | r·m+fr | rv64q rv128q | | # RV128Q "RV128Q Standard Extension for Quadruple-Precision Floating-Point (in addition to RV64Q)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |fmv.x.q | rd frs1 | r+rf | rv64q rv128q | | |fmv.q.x | frd rs1 | r+fr | rv64q rv128q | | # RV32C "RV32C Standard Extension for Compressed Instructions" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |c.addi4spn|crdq cimm4spn | ciw·4spn | rv32c rv64c | | |c.fld | cfrdq crs1q cimmd | cl·ld+f | rv32c rv64c | | |c.lw | crdq crs1q cimmw | cl·lw | rv32c rv64c | | |c.flw | cfrdq crs1q cimmw | cl·lw+f | rv32c | | |c.fsd | crs1q cfrs2q cimmd | cs·sd+f | rv32c rv64c | | |c.sw | crs1q crs2q cimmw | cs·sw | rv32c rv64c | | |c.fsw | crs1q cfrs2q cimmw | cs·sw+f | rv32c | | |c.nop | | ci·none | rv32c rv64c | | |c.addi | crs1rd cnzimmi | ci | rv32c rv64c | | |c.jal | cimmj | cj·jal | rv32c | | |c.li | crs1rd cimmi | ci·li | rv32c rv64c | | |c.addi16sp|crs1rd cimm16sp | ci·16sp | rv32c rv64c | | |c.lui | crd cimmui | ci·lui | rv32c rv64c | | |c.srli | crs1rdq cimmsh5 | cb·sh5 | rv32c | | |c.srai | crs1rdq cimmsh5 | cb·sh5 | rv32c | | |c.andi | crs1rdq cnzimmi | cb·imm | rv32c rv64c | | |c.sub | crs1rdq crs2q | cs | rv32c rv64c | | |c.xor | crs1rdq crs2q | cs | rv32c rv64c | | |c.or | crs1rdq crs2q | cs | rv32c rv64c | | |c.and | crs1rdq crs2q | cs | rv32c rv64c | | |c.subw | crs1rdq crs2q | cs | rv32c rv64c | | |c.addw | crs1rdq crs2q | cs | rv32c rv64c | | |c.j | cimmj | cj | rv32c rv64c | | |c.beqz | crs1q cimmb | cb | rv32c rv64c | | |c.bnez | crs1q cimmb | cb | rv32c rv64c | | |c.slli | crs1rd cimmsh5 | ci·sh5 | rv32c | | |c.fldsp | cfrd cimmldsp | ci·ldsp+f | rv32c rv64c | | |c.lwsp | crd cimmlwsp | ci·lwsp | rv32c rv64c | | |c.flwsp | cfrd cimmlwsp | ci·lwsp+f | rv32c | | |c.jr | crd0 crs1 | cr·jr | rv32c rv64c | | |c.mv | crd crs2 | cr·mv | rv32c rv64c | | |c.ebreak | | ci·none | rv32c rv64c | | |c.jalr | crd0 crs1 | cr·jalr | rv32c rv64c | | |c.add | crs1rd crs2 | cr | rv32c rv64c | | |c.fsdsp | cfrs2 cimmsdsp | css·sdsp+f | rv32c rv64c | | |c.swsp | crs2 cimmswsp | css·swsp | rv32c rv64c | | |c.fswsp | cfrs2 cimmswsp | css·swsp+f | rv32c | | # RV64C "RV64C Standard Extension for Compressed Instructions (in addition to RV32C)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |c.ld | crdq crs1q cimmd | cl·ld | rv64c | | |c.sd | crs1q crs2q cimmd | cs·sd | rv64c | | |c.addiw | crs1rd cimmi | ci | rv64c | | |c.srli | crs1rdq cimmsh6 | cb·sh6 | rv64c | | |c.srai | crs1rdq cimmsh6 | cb·sh6 | rv64c | | |c.slli | crs1rd cimmsh6 | ci·sh6 | rv64c | | |c.ldsp | crd cimmldsp | ci·ldsp | rv64c | | |c.sdsp | crs2 cimmsdsp | css·sdsp | rv64c | | # RV128C "RV128C Standard Extension for Compressed Instructions (in addition to RV64C)" | (23..18) | (17..12) | (11..6) | (5...0) | | | -------- | -------- | ------- | ------- | | |c.lq | crdq crs1q cimmq | cl·lq | rv128c | | |c.sq | crs1q crs2q cimmq | cs·sq | rv128c | | |c.lqsp | crd cimmlqsp | ci·lqsp | rv128c | | |c.sqsp | crs2 cimmsqsp | css·sqsp | rv128c | |