[[!oldstandards]]
# Variable-width Variable-packed SIMD / Simple-V / Parallelism Extension Proposal
**OBSOLETE. This document is out of date and involved early ideas and discussions. [Go to the up-to-date document](https://libre-soc.org/openpower/sv/)**
# References
* SIMD considered harmful
* Link to first proposal
* Recommendation by Jacob Bachmeyer to make zero-overhead loop an
"implicit program-counter"
* Re-continuing P-Extension proposal
* First Draft P-SIMD (DSP) proposal
* B-Extension discussion
* Broadcom VideoCore-IV
Figure 2 P17 and Section 3 on P16.
* Hwacha
* Hwacha
* Vector Workshop
* Predication
* Branch Divergence
* Life of Triangles (3D)
* Videocore-IV
* Discussion proposing CSRs that change ISA definition
* Zero-overhead loops
* Multi-ported VLIW Register File Implementation
* Fast context save/restore proposal
* Register File Bank Cacheing
* Expired Patent on Vector Virtual Memory solutions
* Discussion on RVV "re-entrant" capabilities allowing operations to be
restarted if an exception occurs (VM page-table miss)
* Dot Product Vector
* RVV slides 2017
* Wavefront skipping using BRAMS
* Streaming Pipelines
* Barcelona SIMD Presentation
*
* Full Description (last page) of RVV instructions
* PULP Low-energy Cluster Vector Processor