# NB: Box inputs/outputs must each be in the same order
#     as their corresponding module definition
#     (with exceptions detailed below)

# Box 1 : CCU2C (2xCARRY + 2xLUT4)
#   (Exception: carry chain input/output must be the
#        last input and output and the entire bus has been
#        moved there overriding the otherwise
#        alphabetical ordering)
# name  ID   w/b   ins    outs
CCU2C   1      1   9      3
#A0  B0   C0    D0   A1   B1   C1   D1   CIN
379  379  275   141  -    -    -    -    257 # S0
630  630  526   392  379  379  275  141  273 # S1
516  516  412   278  516  516  412  278   43 # COUT

# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
# name               ID  w/b   ins   outs
$__ABC9_DPR16X4_COMB  2     0   8    4
#$DO0 $DO1 $DO2 $DO3 RAD0   RAD1   RAD2   RAD3
0     0    0    0    141    379    275    379 # DO0
0     0    0    0    141    379    275    379 # DO1
0     0    0    0    141    379    275    379 # DO2
0     0    0    0    141    379    275    379 # DO3

# Box 3 : PFUMX (MUX2)
# name  ID   w/b   ins    outs
PFUMX   3    1     3      1
#ALUT  BLUT  C0
98     98    151 # Z

# Box 4 : L6MUX21 (MUX2)
# name   ID   w/b   ins    outs
L6MUX21  4    1     3      1
#D0    D1    SD
140    141   148 # Z