---------- Begin Simulation Statistics ---------- sim_seconds 2.582494 # Number of seconds simulated sim_ticks 2582494330500 # Number of ticks simulated final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 58235 # Simulator instruction rate (inst/s) host_tick_rate 1883208568 # Simulator tick rate (ticks/s) host_mem_usage 413296 # Number of bytes of host memory used host_seconds 1371.33 # Real time elapsed on the host sim_insts 79859495 # Number of instructions simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory system.nvmem.num_reads 6 # Number of read requests responded to by this memory system.nvmem.num_writes 0 # Number of write requests responded to by this memory system.nvmem.num_other 0 # Number of other requests responded to by this memory system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read 131499364 # Number of bytes read from this memory system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory system.physmem.bytes_written 10236688 # Number of bytes written to this memory system.physmem.num_reads 15129208 # Number of read requests responded to by this memory system.physmem.num_writes 869902 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 132156 # number of replacements system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use system.l2c.total_refs 1820044 # Total number of references to valid blocks. system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::0 4997.961622 # Average occupied blocks per context system.l2c.occ_blocks::1 7175.690427 # Average occupied blocks per context system.l2c.occ_blocks::2 15403.191755 # Average occupied blocks per context system.l2c.occ_percent::0 0.076263 # Average percentage of cache occupancy system.l2c.occ_percent::1 0.109492 # Average percentage of cache occupancy system.l2c.occ_percent::2 0.235034 # Average percentage of cache occupancy system.l2c.ReadReq_hits::0 739066 # number of ReadReq hits system.l2c.ReadReq_hits::1 627724 # number of ReadReq hits system.l2c.ReadReq_hits::2 184257 # number of ReadReq hits system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits system.l2c.Writeback_hits::0 599046 # number of Writeback hits system.l2c.Writeback_hits::total 599046 # number of Writeback hits system.l2c.UpgradeReq_hits::0 992 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::1 1000 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::1 443 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::0 58603 # number of ReadExReq hits system.l2c.ReadExReq_hits::1 38925 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits system.l2c.demand_hits::0 797669 # number of demand (read+write) hits system.l2c.demand_hits::1 666649 # number of demand (read+write) hits system.l2c.demand_hits::2 184257 # number of demand (read+write) hits system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits system.l2c.overall_hits::0 797669 # number of overall hits system.l2c.overall_hits::1 666649 # number of overall hits system.l2c.overall_hits::2 184257 # number of overall hits system.l2c.overall_hits::total 1648575 # number of overall hits system.l2c.ReadReq_misses::0 19787 # number of ReadReq misses system.l2c.ReadReq_misses::1 20563 # number of ReadReq misses system.l2c.ReadReq_misses::2 170 # number of ReadReq misses system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses system.l2c.UpgradeReq_misses::0 7351 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 3816 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 849 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::1 448 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::0 97885 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 50394 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses system.l2c.demand_misses::0 117672 # number of demand (read+write) misses system.l2c.demand_misses::1 70957 # number of demand (read+write) misses system.l2c.demand_misses::2 170 # number of demand (read+write) misses system.l2c.demand_misses::total 188799 # number of demand (read+write) misses system.l2c.overall_misses::0 117672 # number of overall misses system.l2c.overall_misses::1 70957 # number of overall misses system.l2c.overall_misses::2 170 # number of overall misses system.l2c.overall_misses::total 188799 # number of overall misses system.l2c.ReadReq_miss_latency 2117109000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 60330000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency 7673500 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency 7779101999 # number of ReadExReq miss cycles system.l2c.demand_miss_latency 9896210999 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency 9896210999 # number of overall miss cycles system.l2c.ReadReq_accesses::0 758853 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::1 648287 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::2 184427 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::0 599046 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::0 8343 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 4816 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 1024 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::1 891 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 156488 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 89319 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::0 915341 # number of demand (read+write) accesses system.l2c.demand_accesses::1 737606 # number of demand (read+write) accesses system.l2c.demand_accesses::2 184427 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses system.l2c.overall_accesses::0 915341 # number of overall (read+write) accesses system.l2c.overall_accesses::1 737606 # number of overall (read+write) accesses system.l2c.overall_accesses::2 184427 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::0 0.026075 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::1 0.031719 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.000922 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.058716 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::0 0.881098 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 0.792359 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::0 0.829102 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::1 0.502806 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::0 0.625511 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 0.564202 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::0 0.128555 # miss rate for demand accesses system.l2c.demand_miss_rate::1 0.096199 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.000922 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.225676 # miss rate for demand accesses system.l2c.overall_miss_rate::0 0.128555 # miss rate for overall accesses system.l2c.overall_miss_rate::1 0.096199 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.000922 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.225676 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::0 106994.946177 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 102957.204688 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 12453582.352941 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 12663534.503806 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::0 8207.046660 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::0 9038.280330 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::0 79471.849609 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 154365.638747 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::0 84099.964299 # average overall miss latency system.l2c.demand_avg_miss_latency::1 139467.719873 # average overall miss latency system.l2c.demand_avg_miss_latency::2 58213005.876471 # average overall miss latency system.l2c.demand_avg_miss_latency::total 58436573.560642 # average overall miss latency system.l2c.overall_avg_miss_latency::0 84099.964299 # average overall miss latency system.l2c.overall_avg_miss_latency::1 139467.719873 # average overall miss latency system.l2c.overall_avg_miss_latency::2 58213005.876471 # average overall miss latency system.l2c.overall_avg_miss_latency::total 58436573.560642 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks 112618 # number of writebacks system.l2c.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 97 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 97 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses 40423 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses 11167 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses 1297 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses 148279 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses 188702 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses 188702 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency 1619864500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency 446963000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency 51939000 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency 5941339999 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency 7561204499 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency 7561204499 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency 131964916000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency 32535008680 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency 164499924680 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::0 0.053269 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 0.062354 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 0.219182 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.334804 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::0 1.338487 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 2.318729 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.266602 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.455668 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::0 0.947542 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 1.660106 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::0 0.206155 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 0.255830 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 1.023180 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 1.485165 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::0 0.206155 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 0.255830 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 1.023180 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 1.485165 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency 40072.842194 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40025.342527 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40045.489591 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40068.654354 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 42410626 # DTB read hits system.cpu0.dtb.read_misses 55840 # DTB read misses system.cpu0.dtb.write_hits 6900244 # DTB write hits system.cpu0.dtb.write_misses 11203 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 42466466 # DTB read accesses system.cpu0.dtb.write_accesses 6911447 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 49310870 # DTB hits system.cpu0.dtb.misses 67043 # DTB misses system.cpu0.dtb.accesses 49377913 # DTB accesses system.cpu0.itb.inst_hits 6428492 # ITB inst hits system.cpu0.itb.inst_misses 17283 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses system.cpu0.itb.hits 6428492 # DTB hits system.cpu0.itb.misses 17283 # DTB misses system.cpu0.itb.accesses 6445775 # DTB accesses system.cpu0.numCycles 352483912 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued system.cpu0.iq.rate 0.227743 # Inst issue rate system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 506934 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 642786 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 173953 # number of nop insts executed system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed system.cpu0.iew.exec_branches 6431362 # Number of branches executed system.cpu0.iew.exec_stores 7171156 # Number of stores executed system.cpu0.iew.exec_rate 0.225691 # Inst execution rate system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back system.cpu0.iew.wb_producers 24791862 # num instructions producing a value system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle system.cpu0.commit.count 41923639 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 15936098 # Number of memory references committed system.cpu0.commit.loads 9243307 # Number of loads committed system.cpu0.commit.membars 288653 # Number of memory barriers committed system.cpu0.commit.branches 5542289 # Number of branches committed system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. system.cpu0.commit.function_calls 620184 # Number of function calls committed. system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu0.rob.rob_reads 157931724 # The number of ROB reads system.cpu0.rob.rob_writes 106372981 # The number of ROB writes system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 41797812 # Number of Instructions Simulated system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads system.cpu0.ipc 0.118581 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes system.cpu0.icache.replacements 538787 # number of replacements system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::0 5838964 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits system.cpu0.icache.demand_hits::0 5838964 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits system.cpu0.icache.overall_hits::0 5838964 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits system.cpu0.icache.overall_hits::total 5838964 # number of overall hits system.cpu0.icache.ReadReq_misses::0 583385 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses system.cpu0.icache.demand_misses::0 583385 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses system.cpu0.icache.overall_misses::0 583385 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses system.cpu0.icache.overall_misses::total 583385 # number of overall misses system.cpu0.icache.ReadReq_miss_latency 8740145988 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency 8740145988 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency 8740145988 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::0 6422349 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::0 6422349 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::0 6422349 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::0 0.090837 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::0 0.090837 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::0 0.090837 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks 29665 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits 44065 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits 44065 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits 44065 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses 539320 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses 539320 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses 539320 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency 6552239991 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency 6552239991 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency 6552239991 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083976 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::0 0.083976 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::0 0.083976 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12149.076598 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 372182 # number of replacements system.cpu0.dcache.tagsinuse 487.975562 # Cycle average of tags in use system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::0 487.992960 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -0.017397 # Average occupied blocks per context system.cpu0.dcache.occ_percent::0 0.953111 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.000034 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::0 7966835 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::0 4346487 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::0 221211 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::0 199868 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::0 12313322 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::0 12313322 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits system.cpu0.dcache.ReadReq_misses::0 463412 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::0 1864293 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::0 10042 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::0 7686 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::0 2327705 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::0 2327705 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency 6478995500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency 70420524827 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency 122158000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency 87202500 # number of StoreCondReq miss cycles system.cpu0.dcache.demand_miss_latency 76899520327 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency 76899520327 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::0 8430247 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::0 6210780 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::0 231253 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::0 207554 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::0 14641027 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::0 14641027 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::0 0.054970 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::0 0.300171 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043424 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037031 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::0 0.158985 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::0 0.158985 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks 327766 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses 7685 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses 417836 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses 417836 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency 6370530485 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 87975000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency 64109000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency 9313590485 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency 9313590485 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038766498 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028413 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028709 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.042049 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::0 0.028539 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::0 0.028539 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9047.202797 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8342.094990 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 10576968 # DTB read hits system.cpu1.dtb.read_misses 41875 # DTB read misses system.cpu1.dtb.write_hits 5530754 # DTB write hits system.cpu1.dtb.write_misses 15302 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 10618843 # DTB read accesses system.cpu1.dtb.write_accesses 5546056 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 16107722 # DTB hits system.cpu1.dtb.misses 57177 # DTB misses system.cpu1.dtb.accesses 16164899 # DTB accesses system.cpu1.itb.inst_hits 8214514 # ITB inst hits system.cpu1.itb.inst_misses 3039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses system.cpu1.itb.hits 8214514 # DTB hits system.cpu1.itb.misses 3039 # DTB misses system.cpu1.itb.accesses 8217553 # DTB accesses system.cpu1.numCycles 69079827 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued system.cpu1.iq.rate 0.728958 # Inst issue rate system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 50586 # number of nop insts executed system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed system.cpu1.iew.exec_branches 5808702 # Number of branches executed system.cpu1.iew.exec_stores 5821790 # Number of stores executed system.cpu1.iew.exec_rate 0.688543 # Inst execution rate system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back system.cpu1.iew.wb_producers 24255669 # num instructions producing a value system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle system.cpu1.commit.count 38086237 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 12651383 # Number of memory references committed system.cpu1.commit.loads 7112761 # Number of loads committed system.cpu1.commit.membars 148646 # Number of memory barriers committed system.cpu1.commit.branches 4805168 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. system.cpu1.commit.function_calls 433251 # Number of function calls committed. system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu1.rob.rob_reads 102142645 # The number of ROB reads system.cpu1.rob.rob_writes 116493771 # The number of ROB writes system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.committedInsts 38061683 # Number of Instructions Simulated system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes system.cpu1.icache.replacements 485586 # number of replacements system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::0 498.788681 # Average occupied blocks per context system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::0 7684975 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits system.cpu1.icache.demand_hits::0 7684975 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits system.cpu1.icache.overall_hits::0 7684975 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits system.cpu1.icache.overall_hits::total 7684975 # number of overall hits system.cpu1.icache.ReadReq_misses::0 527035 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses system.cpu1.icache.demand_misses::0 527035 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses system.cpu1.icache.overall_misses::0 527035 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses system.cpu1.icache.overall_misses::total 527035 # number of overall misses system.cpu1.icache.ReadReq_miss_latency 7752735997 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency 7752735997 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency 7752735997 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::0 8212010 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::0 8212010 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::0 8212010 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::0 0.064179 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::0 0.064179 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::0 0.064179 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks 18538 # number of writebacks system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits system.cpu1.icache.demand_mshr_hits 40914 # number of demand (read+write) MSHR hits system.cpu1.icache.overall_mshr_hits 40914 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses 486121 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses 486121 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency 5799471497 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::0 0.059196 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::0 0.059196 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 272200 # number of replacements system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::0 7085363 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::0 3139669 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::0 75360 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::0 72622 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::0 10225032 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::0 10225032 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits system.cpu1.dcache.ReadReq_misses::0 323287 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::0 1273508 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::0 12669 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::0 11046 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::0 1596795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::0 1596795 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency 5044696500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency 46343696337 # number of WriteReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency 148164500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency 87512500 # number of StoreCondReq miss cycles system.cpu1.dcache.demand_miss_latency 51388392837 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency 51388392837 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::0 7408650 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::0 4413177 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::0 88029 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::0 83668 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::0 11821827 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::0 11821827 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::0 0.043636 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::0 0.288569 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.143918 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132022 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::0 0.135072 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::0 0.135072 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks 223077 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits 1157260 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits system.cpu1.dcache.demand_mshr_hits 1291206 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits 1291206 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency 2489937000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99179500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54297000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency 5942801547 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455613500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41497603581 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency 49953217081 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026341 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132022 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::0 0.025850 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::0 0.025850 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits system.iocache.demand_misses::0 0 # number of demand (read+write) misses system.iocache.demand_misses::1 0 # number of demand (read+write) misses system.iocache.demand_misses::total 0 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 0 # number of overall misses system.iocache.overall_misses::total 0 # number of overall misses system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency 0 # number of overall miss cycles system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks 0 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed ---------- End Simulation Statistics ----------