---------- Begin Simulation Statistics ---------- sim_seconds 0.417996 # Number of seconds simulated sim_ticks 417996021500 # Number of ticks simulated final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 98610 # Simulator instruction rate (inst/s) host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) host_tick_rate 49848381 # Simulator tick rate (ticks/s) host_mem_usage 430328 # Number of bytes of host memory used host_seconds 8385.35 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 386930 # Number of read requests accepted system.physmem.writeReqs 294035 # Number of write requests accepted system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 24110 # Per bank write bursts system.physmem.perBankRdBursts::1 26511 # Per bank write bursts system.physmem.perBankRdBursts::2 24689 # Per bank write bursts system.physmem.perBankRdBursts::3 24586 # Per bank write bursts system.physmem.perBankRdBursts::4 23301 # Per bank write bursts system.physmem.perBankRdBursts::5 23773 # Per bank write bursts system.physmem.perBankRdBursts::6 24463 # Per bank write bursts system.physmem.perBankRdBursts::7 24300 # Per bank write bursts system.physmem.perBankRdBursts::8 23625 # Per bank write bursts system.physmem.perBankRdBursts::9 23952 # Per bank write bursts system.physmem.perBankRdBursts::10 24787 # Per bank write bursts system.physmem.perBankRdBursts::11 24070 # Per bank write bursts system.physmem.perBankRdBursts::12 23353 # Per bank write bursts system.physmem.perBankRdBursts::13 22981 # Per bank write bursts system.physmem.perBankRdBursts::14 24097 # Per bank write bursts system.physmem.perBankRdBursts::15 23979 # Per bank write bursts system.physmem.perBankWrBursts::0 18543 # Per bank write bursts system.physmem.perBankWrBursts::1 19847 # Per bank write bursts system.physmem.perBankWrBursts::2 18947 # Per bank write bursts system.physmem.perBankWrBursts::3 18939 # Per bank write bursts system.physmem.perBankWrBursts::4 18047 # Per bank write bursts system.physmem.perBankWrBursts::5 18457 # Per bank write bursts system.physmem.perBankWrBursts::6 18996 # Per bank write bursts system.physmem.perBankWrBursts::7 18981 # Per bank write bursts system.physmem.perBankWrBursts::8 18548 # Per bank write bursts system.physmem.perBankWrBursts::9 18168 # Per bank write bursts system.physmem.perBankWrBursts::10 18839 # Per bank write bursts system.physmem.perBankWrBursts::11 17728 # Per bank write bursts system.physmem.perBankWrBursts::12 17372 # Per bank write bursts system.physmem.perBankWrBursts::13 16973 # Per bank write bursts system.physmem.perBankWrBursts::14 17820 # Per bank write bursts system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 417995980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 386930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 294035 # Write request sizes (log2) system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads system.physmem.totQLat 4282714250 # Total ticks spent queuing system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing system.physmem.readRowHits 318033 # Number of row buffer hits during reads system.physmem.writeRowHits 215097 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes system.physmem.avgGap 613828.88 # Average gap between requests system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) system.physmem_0.averagePower 692.167087 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) system.physmem_1.averagePower 691.276862 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 230262495 # Number of BP lookups system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 835992044 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued system.cpu.iq.rate 2.185458 # Inst issue rate system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed system.cpu.iew.exec_branches 171793179 # Number of branches executed system.cpu.iew.exec_stores 170131277 # Number of stores executed system.cpu.iew.exec_rate 2.159821 # Inst execution rate system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back system.cpu.iew.wb_producers 1367992688 # num instructions producing a value system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262343 # Number of memory references committed system.cpu.commit.loads 384102157 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached system.cpu.rob.rob_reads 2782646702 # The number of ROB reads system.cpu.rob.rob_writes 4280772798 # The number of ROB writes system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes system.cpu.fp_regfile_reads 7563 # number of floating regfile reads system.cpu.fp_regfile_writes 476 # number of floating regfile writes system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 2534281 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits system.cpu.dcache.overall_hits::total 387196758 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses system.cpu.dcache.overall_misses::total 3775006 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks system.cpu.dcache.writebacks::total 2332980 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7107 # number of replacements system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits system.cpu.icache.overall_hits::total 179317997 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses system.cpu.icache.overall_misses::total 208472 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 354249 # number of replacements system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.903915 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13370 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18660 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41777056 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41777056 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 5192 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1590453 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1595645 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2332980 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2332980 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1881 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1881 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 564507 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 564507 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 5192 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 2154960 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2160152 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5192 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 2154960 # number of overall hits system.cpu.l2cache.overall_hits::total 2160152 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3552 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 176400 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 179952 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 195096 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 195096 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 207017 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 207017 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3552 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 383417 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 386969 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3552 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 383417 # number of overall misses system.cpu.l2cache.overall_misses::total 386969 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294540500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275679000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 14570219500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13220077 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 13220077 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16430030463 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 16430030463 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 294540500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 30705709463 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 31000249963 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 294540500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 30705709463 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 31000249963 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8744 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1766853 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1775597 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2332980 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2332980 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196977 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 196977 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 771524 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 771524 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 8744 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2538377 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2547121 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 8744 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2538377 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2547121 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406221 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099839 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.101347 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990451 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990451 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268322 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.268322 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406221 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.151048 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.151048 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 67.761907 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 67.761907 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 294035 # number of writebacks system.cpu.l2cache.writebacks::total 294035 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 197098 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 179950 # Transaction distribution system.membus.trans_dist::ReadResp 179949 # Transaction distribution system.membus.trans_dist::Writeback 294035 # Transaction distribution system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution system.membus.trans_dist::ReadExReq 206980 # Transaction distribution system.membus.trans_dist::ReadExResp 206980 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 876098 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 876098 # Request fanout histogram system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ----------