/*
- * Copyright (c) 2004 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* @file
- * Defines a 8250 UART
+/** @file
+ * Base class for UART
*/
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
+#ifndef __UART_HH__
+#define __UART_HH__
-#include "dev/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
class Uart : public PioDevice
{
- private:
+ protected:
+ int status;
Addr addr;
Addr size;
SimConsole *cons;
-
- protected:
- int readAddr; // tlaser only
- uint8_t IER, DLAB, LCR, MCR;
- int status;
-
- class IntrEvent : public Event
- {
- protected:
- Uart *uart;
- int intrBit;
- public:
- IntrEvent(Uart *u, int bit);
- virtual void process();
- virtual const char *description();
- void scheduleIntr();
- };
-
- IntrEvent txIntrEvent;
- IntrEvent rxIntrEvent;
- Platform *platform;
-
public:
- Uart(const string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *bus, Platform *p);
+ Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
+ Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
+ Platform *p);
- Fault read(MemReqPtr &req, uint8_t *data);
- Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
+ virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
/**
* Inform the uart that there is data available.
*/
- void dataAvailable();
+ virtual void dataAvailable() = 0;
/**
*/
bool intStatus() { return status ? true : false; }
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
-
/**
* Return how long this access will take.
* @param req the memory request to calcuate
Tick cacheAccess(MemReqPtr &req);
};
-#endif // __TSUNAMI_UART_HH__
+#endif // __UART_HH__