case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+ case PIPE_CAP_TILE_RASTER_ORDER:
+ case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
return 0;
/* Stream output. */
/* Timer queries. */
case PIPE_CAP_QUERY_TIME_ELAPSED:
- case PIPE_CAP_OCCLUSION_QUERY:
return 0;
+ case PIPE_CAP_OCCLUSION_QUERY:
+ return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
case PIPE_CAP_QUERY_TIMESTAMP:
return 1;
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
case PIPE_SHADER_CAP_INTEGERS:
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
+ case PIPE_SHADER_CAP_FP16:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 4096;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return false;
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
+ if (util_format_is_srgb(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
+
if (fmt & EXT_FORMAT) {
supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
screen->specs.has_new_transcendentals =
VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
+ screen->specs.has_halti2_instructions =
+ VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
/* GC3000 - this core is capable of loading shaders from