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Add opt_ffinv pass.
[yosys.git]
/
techlibs
/
coolrunner2
/
cells_counter_map.v
diff --git
a/techlibs/coolrunner2/cells_counter_map.v
b/techlibs/coolrunner2/cells_counter_map.v
index b474fa522005dd69adae6bfe11232bcfe8e1183d..f9c44c80ff20bc7254b600b981c9b9349b1f26e0 100644
(file)
--- a/
techlibs/coolrunner2/cells_counter_map.v
+++ b/
techlibs/coolrunner2/cells_counter_map.v
@@
-3,6
+3,7
@@
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output wire OUT;
+ (* force_downto *)
output wire[WIDTH-1:0] POUT;
input wire RST;
input wire UP;