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verilog: allow spaces in macro arguments
[yosys.git]
/
.editorconfig
diff --git
a/.editorconfig
b/.editorconfig
index 4d6f5ef7abebc3add37b301903ec0b1d9069ae58..f5444d81a749b4181140d5b70bedc4914428e3d4 100644
(file)
--- a/
.editorconfig
+++ b/
.editorconfig
@@
-5,3
+5,8
@@
indent_style = tab
indent_size = tab
trim_trailing_whitespace = true
insert_final_newline = true
indent_size = tab
trim_trailing_whitespace = true
insert_final_newline = true
+
+[abc/**]
+indent_style = space
+indent_size = 2
+trim_trailing_whitespace = false