+You need to understand what gates are. look up AND, OR, XOR, NOT, NAND,
+NOR, MUX, DFF, SR latch on electronics forums and wikipedia. also look up
+"register latches", then HALF ADDER and FULL ADDER. If you would like a
+particularly amusing relevant distraction, look up the guy who built an
+entire functional computer out of 74 series logic chips, on breadboards.
+It's now in a museum.
+
+For some reason, ASIC designers call collections of gates (such as MUXers)
+"Cells", no matter how large they are. There are some more complex
+"Cells" such as "4-input MUX" or "3-input XOR" and so on, which should
+be self-explanatory. Thus you will see the words "Cell Library" used.
+
+Yes you can create your own cell libraries, however you will also see
+Foundries refer to things called "Standard Cell Libraries" which they
+expect you to use (under NDA. sigh).
+
+Also look up "boolean algebra", "Karnaugh maps", truth tables and things
+like that.
+
+From there you can begin to appreciate how deeply ridiculously low level
+this all is, and why we are using nmigen. nmigen constructs "useful"
+concepts like "32 bit numbers", which actually do not exist at the gate
+level: they only exist by way of being constructed from chains of 1 bit
+(binary) processing!
+
+So for example, a 32 bit adder is "constructed" from a batch of 32 FULL
+ADDERs (actually, 31 FULL and one HALF). Even things like comparing
+two numbers, the simple "==" or ">=" operators, are done entirely with
+a bit-level cascade!
+
+This would drive you nuts if you had to think at this level all the time,
+consequently "High" in "High Level Language" was invented. Luckily in
+python, you can override \_\_add\_\_ and so on in order that when you put
+"a + b" into a nmigen program it gives you the *impression* that two
+"actual" numbers are being added, whereas in fact you requested that
+the HDL create a massive bunch of "gates" on your behalf.
+
+i.e. *behind the scenes* the HDL uses "cells" that in a massive
+hierarchical cascade ultimately end up at nothing more than "gates".
+
+Yes you really do need to know this because those "gates" cost both
+power, space, and take time to switch. So if you have too many of them
+in a chain, your chip is limited in its top speed. This is the point
+at which you should be looking up "pipelines" and "register latches",
+as well as "combinatorial blocks".
+
+you also want to look up the concept of a FSM (Finite State Machine)
+and the difference between a Mealy and a Moore FSM.
+
+## NDAs...
+
+These are a nuisance. There are around 4 levels of NDAs to bust through:
+Full chip designs, peripherals and other third party components, Cell
+Libraries, and Foundries. Often, the Foundries supply their own Standard
+Cell Libraries (see above).
+
+Sometimes you want to design something not under NDA (as we do), but
+in order to do so you still need to know the "shape" of the Cells.
+Occasionally, then, the licensee of those Cells will allow you to use
+"phantoms", which are the same shape and have the same connections.
+The official Industry term for these is "phantom views". See
+<http://bugs.libre-riscv.org/show_bug.cgi?id=178#c106> for discussion.
+
+Then there are also "abstract" views: these are also under NDA.
+So, we will be doing the layout in generic "lambda" design, and a
+conversion pass (under NDA) is carried out which maps to TSMC. See
+<http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/004804.html>