+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
+* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
+* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
+* <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
+* <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
+* <https://chips4makers.io/blog/>
+* <https://hackaday.io/project/7817-zynqberry>
+* <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
+* <https://efabless.com/design_catalog/default>
+* <https://toyota-ai.ventures/>
+* <https://github.com/lambdaconcept/minerva>
+
+# Analog Simulation
+
+* <https://github.com/Isotel/mixedsim>
+* <http://www.vlsiacademy.org/open-source-cad-tools.html>
+* <http://ngspice.sourceforge.net/adms.html>
+* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>