+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
+64 bit, single core dual issue, around 300 to 350mhz. This will provide
+the confidence to go to higher geometries, as well as be a commercially
+viable embedded product in its own right. Tapeout deadline is Oct 2020.
+
+See [[3d_gpu/articles]] online.
+
+# Progress:
+
+* Dec 2021 first MMU unit tests pass, running microwatt mmu.bin.
+ Shows MMU and L1 D/I-Caches as functional in simulation.
+* Apr 2021 cocotb simulation of 180nm ASIC implemented. JTAG TAP
+ confirmed functional on ECP5 and simulation. FreePDK-c4m45
+ created by <https://chips4makers.io>
+* Mar 2021 first SVP64 OpenPOWER augmented Cray-style instructions executed.
+ NGI POINTER EUR 200,000 grant submitted.
+* Feb 2021 FOSDEM2021, Simple-V SVP64 implementation starts in
+ simulator and Test Issuer
+* Jan 2021 FOSDEM2021 talks confirmed, NLnet crypto-primitives proposal
+ submitted, budget agreed for basic binutils and gcc SVP64 support
+* Dec 2020 work on [[openpower/sv/svp64]] started
+* Nov 2020 dry-run 180nm GDSII sent to IMEC
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+ for 180nm test ASIC, GDSII deadline set of Dec 2nd.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
+* Jun 2020: core unit tests and pipeline formal correctness proofs in place.
+* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
+* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
+ exploration started. OpenPOWER ISA decoder started. Two new people:
+ Alain and Jock.
+* Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created.
+* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020
+* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+)
+* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
+* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted.
+* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed.
+* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
+* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV,
+ FCLASS and FCVT pipelines completed.
+* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
+* May 2019: 6600-style scoreboard started