+The lower pincount, lower power, and higher BGA pitch is all to reduce
+the cost of product development when it comes to PCB design and layout:
+
+* Above 4 watts requires metal packages, greater attention to thermal
+ management in the PCB design and layout, and much pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
+ equipment and more costly PCBA techniques.
+* Above 600 pins begins to reduce production yields as well as increase
+ the cost of testing and packaging.
+
+We can look at larger higher-power ASICs either later or, if funding
+is made available, immediately.
+
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
+
+# Business Objectives
+
+* the project shall be a hybrid CPU-GPU because if it is not, the
+ complexity involved in developing a split shared-memory CPU-GPU both
+ at a hardware and a software level will be so costly it will jeapordise
+ the project.
+* the project shall be commercial and mass-volume (100 million units
+ and above)
+* the project shall be entirely transparent so that end-users will be
+ able to trust it
+* the source code shall be available at all times for all components
+ for BUSINESS reasons, making development and use of SDKs dead simple
+ and aiding and assisting developers AND BUSINESSES in debugging and thus
+ hugely saving them money.
+
+# Links: