+ - Added "clkbufmap" pass
+ - Added "extractinv" pass and "invertible_pin" attribute
+ - Added "proc_clean -quiet"
+ - Added "proc_prune" pass
+ - Added "stat -tech cmos"
+ - Added "opt_share" pass, run as part of "opt -full"
+ - Added "-match-init" option to "dff2dffs" pass
+ - Added "equiv_opt -multiclock"
+ - Added "techmap_autopurge" support to techmap
+ - Added "add -mod <modname[s]>"
+ - Added "paramap" pass
+ - Added "portlist" command
+ - Added "check -mapped"
+ - Added "check -allow-tbuf"
+ - Added "autoname" pass
+ - Added "write_verilog -extmem"
+ - Added "opt_mem" pass
+ - Added "scratchpad" pass
+ - Added "fminit" pass
+ - Added "opt_lut_ins" pass
+ - Added "logger" pass
+ - Added "show -nobg"
+ - Added "exec" command
+ - Added "design -delete"
+ - Added "design -push-copy"
+ - Added "qbfsat" command
+ - Added "select -unset"
+ - Added "dfflegalize" pass
+ - Removed "opt_expr -clkinv" option, made it the default
+ - Added "proc -nomux
+ - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
+
+ * SystemVerilog
+ - Added checking of always block types (always_comb, always_latch and always_ff)
+ - Added support for wildcard port connections (.*)
+ - Added support for enum typedefs
+ - Added support for structs and packed unions.
+ - Allow constant function calls in for loops and generate if and case
+ - Added support for static cast
+ - Added support for logic typed parameters
+ - Fixed generate scoping issues
+ - Added support for real-valued parameters
+ - Allow localparams in constant functions
+ - Module name scope support
+ - Support recursive functions using ternary expressions
+ - Extended support for integer types
+ - Support for parameters without default values
+ - Allow globals in one file to depend on globals in another
+ - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
+ - Added support for parsing the 'bind' construct
+ - support declaration in procedural for initialization
+ - support declaration in generate for initialization
+ - Support wand and wor of data types
+
+ * Verific support
+ - Added "verific -L"
+ - Add Verific SVA support for "always" properties
+ - Add Verific support for SVA nexttime properties
+ - Improve handling of verific primitives in "verific -import -V" mode
+ - Import attributes for wires
+ - Support VHDL enums
+ - Added support for command files
+
+ * New back-ends
+ - Added initial EFINIX support
+ - Added Intel ALM: alternative synthesis for Intel FPGAs
+ - Added initial Nexus support
+ - Added initial MachXO2 support
+ - Added initial QuickLogic PolarPro 3 support
+
+ * ECP5 support
+ - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+ - Added "synth_ecp5 -abc9" (experimental)
+ - Added "synth_ecp5 -nowidelut"
+ - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+
+ * iCE40 support
+ - Added "synth_ice40 -abc9" (experimental)
+ - Added "synth_ice40 -device"
+ - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
+ - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
+ - Removed "ice40_unlut"
+ - Added "ice40_dsp" for Lattice iCE40 DSP packing
+ - "synth_ice40 -dsp" to infer DSP blocks
+
+ * Xilinx support
+ - Added "synth_xilinx -abc9" (experimental)