+ - Added $bmux and $demux cells and related optimization patterns.
+
+ * New commands and options
+ - Added "bmuxmap" and "dmuxmap" passes
+ - Added "-fst" option to "sim" pass for writing FST files
+ - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
+ "-sim-gold" options to "sim" pass for co-simulation
+
+ * Anlogic support
+ - Added support for BRAMs
+
+Yosys 0.12 .. Yosys 0.13
+--------------------------
+
+ * Various
+ - Use "read" command to parse HDL files from Yosys command-line
+ - Added "yosys -r <topmodule>" command line option
+ - write_verilog: dump zero width sigspecs correctly
+
+ * SystemVerilog
+ - Fixed regression preventing the use array querying functions in case
+ expressions and case item expressions
+ - Fixed static size casts inadvertently limiting the result width of binary
+ operations
+ - Fixed static size casts ignoring expression signedness
+ - Fixed static size casts not extending unbased unsized literals
+ - Added automatic `nosync` inference for local variables in `always_comb`
+ procedures which are always assigned before they are used to avoid errant
+ latch inference
+
+ * New commands and options
+ - Added "clean_zerowidth" pass
+
+ * Verific support
+ - Add YOSYS to the implicitly defined verilog macros in verific
+
+Yosys 0.11 .. Yosys 0.12
+--------------------------
+
+ * Various
+ - Added iopadmap native support for negative-polarity output enable
+ - ABC update
+
+ * SystemVerilog
+ - Support parameters using struct as a wiretype
+
+ * New commands and options
+ - Added "-genlib" option to "abc" pass
+ - Added "sta" very crude static timing analysis pass
+
+ * Verific support
+ - Fixed memory block size in import
+
+ * New back-ends
+ - Added support for GateMate FPGA from Cologne Chip AG
+
+ * Intel ALM support
+ - Added preliminary Arria V support
+
+
+Yosys 0.10 .. Yosys 0.11
+--------------------------
+
+ * Various
+ - Added $aldff and $aldffe (flip-flops with async load) cells
+
+ * SystemVerilog
+ - Fixed an issue which prevented writing directly to a memory word via a
+ connection to an output port
+ - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
+ filling the width of a cell input
+ - Fixed an issue where connecting a slice covering the entirety of a signed
+ signal to a cell input would cause a failed assertion
+
+ * Verific support
+ - Importer support for {PRIM,WIDE_OPER}_DFF
+ - Importer support for PRIM_BUFIF1
+ - Option to use Verific without VHDL support
+ - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+ - Added -cfg option for getting/setting Verific runtime flags
+
+Yosys 0.9 .. Yosys 0.10
+--------------------------
+
+ * Various
+ - Added automatic gzip decompression for frontends
+ - Added $_NMUX_ cell type
+ - Added automatic gzip compression (based on filename extension) for backends
+ - Improve attribute and parameter encoding in JSON to avoid ambiguities between
+ bit vectors and strings containing [01xz]*
+ - Improvements in pmgen: subpattern and recursive matches
+ - Support explicit FIRRTL properties
+ - Improvements in pmgen: slices, choices, define, generate
+ - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+ - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+ - Added new frontend: rpc
+ - Added --version and -version as aliases for -V
+ - Improve yosys-smtbmc "solver not found" handling
+ - Improved support of $readmem[hb] Memory Content File inclusion
+ - Added CXXRTL backend
+ - Use YosysHQ/abc instead of upstream berkeley-abc/abc
+ - Added WASI platform support.
+ - Added extmodule support to firrtl backend
+ - Added $divfloor and $modfloor cells
+ - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
+ - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
+ - Added firrtl backend support for generic parameters in blackbox components
+ - Added $meminit_v2 cells (with support for write mask)
+ - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
+ - write priority masks, per write/write port pair
+ - transparency and undefined collision behavior masks, per read/write port pair
+ - read port reset and initialization
+ - wide ports (accessing a naturally aligned power-of-two number of memory cells)
+
+ * New commands and options