+ - clk2fflogic: nice names for autogenerated signals
+ - simulation include support for all flip-flop types.
+ - Added AIGER witness file co-simulation.
+
+ * Verilog
+ - Fixed evaluation of constant functions with variables or arguments with
+ reversed dimensions
+ - Fixed elaboration of dynamic range assignments where the vector is
+ reversed or is not zero-indexed
+ - Added frontend support for time scale delay values (e.g., `#1ns`)
+
+ * SystemVerilog
+ - Added support for accessing whole sub-structures in expressions
+
+ * New commands and options
+ - Added glift command, used to create gate-level information flow tracking
+ (GLIFT) models by the "constructive mapping" approach
+
+ * Verific support
+ - Ability to override default parser mode for verific -f command.
+
+Yosys 0.13 .. Yosys 0.14
+--------------------------
+
+ * Various
+ - Added $bmux and $demux cells and related optimization patterns.
+
+ * New commands and options
+ - Added "bmuxmap" and "dmuxmap" passes
+ - Added "-fst" option to "sim" pass for writing FST files
+ - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
+ "-sim-gold" options to "sim" pass for co-simulation
+
+ * Anlogic support
+ - Added support for BRAMs
+
+Yosys 0.12 .. Yosys 0.13
+--------------------------
+
+ * Various
+ - Use "read" command to parse HDL files from Yosys command-line
+ - Added "yosys -r <topmodule>" command line option
+ - write_verilog: dump zero width sigspecs correctly