+Yosys 0.13 .. Yosys 0.13-dev
+--------------------------
+
+Yosys 0.12 .. Yosys 0.13
+--------------------------
+
+ * Various
+ - Use "read" command to parse HDL files from Yosys command-line
+ - Added "yosys -r <topmodule>" command line option
+ - write_verilog: dump zero width sigspecs correctly
+
+ * SystemVerilog
+ - Fixed regression preventing the use array querying functions in case
+ expressions and case item expressions
+ - Fixed static size casts inadvertently limiting the result width of binary
+ operations
+ - Fixed static size casts ignoring expression signedness
+ - Fixed static size casts not extending unbased unsized literals
+ - Added automatic `nosync` inference for local variables in `always_comb`
+ procedures which are always assigned before they are used to avoid errant
+ latch inference
+
+ * New commands and options
+ - Added "clean_zerowidth" pass
+
+ * Verific support
+ - Add YOSYS to the implicitly defined verilog macros in verific
+
+Yosys 0.11 .. Yosys 0.12
+--------------------------
+
+ * Various
+ - Added iopadmap native support for negative-polarity output enable
+ - ABC update
+
+ * SystemVerilog
+ - Support parameters using struct as a wiretype
+
+ * New commands and options
+ - Added "-genlib" option to "abc" pass
+ - Added "sta" very crude static timing analysis pass
+
+ * Verific support
+ - Fixed memory block size in import
+
+ * New back-ends
+ - Added support for GateMate FPGA from Cologne Chip AG
+
+ * Intel ALM support
+ - Added preliminary Arria V support
+
+
+Yosys 0.10 .. Yosys 0.11