+8. LDSTCompUnit parallel functions unit test
+ <https://bugs.libre-soc.org/show_bug.cgi?id=350>
+ Priority: Medium-ish
+
+11. Formal Proof for CompUnit
+ <https://bugs.libre-soc.org/show_bug.cgi?id=342>
+
+12. Formal Proof for PartitionedSignal
+ <https://bugs.libre-soc.org/show_bug.cgi?id=565>
+ Status: in progress
+
+13. Implement simple VL for-loop in nMigen for TestIssuer
+ <https://bugs.libre-soc.org/show_bug.cgi?id=583>
+ Status: in progress
+
+## Completed but not yet submitted:
+
+1. FSM-based ALU example needed (compliant with ALU CompUnit)
+ <https://bugs.libre-soc.org/show_bug.cgi?id=417>
+
+2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder
+ <https://bugs.libre-soc.org/show_bug.cgi?id=600>
+
+## Submitted for NLNet RFP
+
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+ Implement simple VL for\-loop in nMigen for TestIssuer
+ * €2325 which is the total amount
+ * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+ Improve formal verification on PartitionedSignal
+ * €2200 out of total of €3000
+ * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+ add SVP64 to PowerDecoder2
+ * €300 out of total of €1000
+ * submitted on 2022-06-16
+
+## Paid
+
+### NLNet.2019.10.043.Wishbone
+
+* [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
+ cxxsim improvements
+ * Ran several Libre-SOC tests under cxxsim
+ * Helped isolate simulator issues by extracting a MVCE
+(Minimal, Verifiable, Complete Example) in each case.
+ * paid on 2021-05-11
+ * €250 out of total of €1750