+
+## qemu, cross-compilers, gdb
+
+As we are doing POWER ISA, POWER ISA compilers, toolchains and
+emulators are required.
+
+Install powerpc64 gcc:
+
+ apt-get install gcc-9-powerpc64-linux-gnu
+
+Install qemu:
+
+ apt-get install qemu-system-ppc
+
+Install gdb from source. Obtain the latest tarball, unpack it, then:
+
+ cd gdb-9.1 (or other location)
+ mkdir build
+ cd build
+ ../configure --srcdir=.. --host=x86_64-linux --target=powerpc64-linux-gnu
+ make -j$(nproc)
+ make install
+
+## power_instruction_analyzer (pia)
+
+We have a custom tool built in rust by programmerjake to help analyze
+the power instructions execution on *actual* hardware.
+
+Note: a very recent version of pip3 is required for this to work.
+
+Install rust:
+
+ curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
+
+Make sure we have the correct and up-to-date rust compiler (rustc):
+
+ rustup default stable
+ rustup update
+
+Use rust's package manager *cargo* to install the rust-python build tool maturin:
+
+ cargo install maturin
+
+Install from git source by doing the following:
+
+ git clone https://salsa.debian.org/Kazan-team/power-instruction-analyzer.git pia
+ cd pia
+ maturin build --cargo-extra-args=--features=python-extension
+ python3 -m pip install --user target/wheels/*.whl
+
+Note: an ongoing bug in maturin interferes with successful installation. This can be worked around by explicitly installing only the .whl files needed rather than installing everything (*.whl).
+
+## Coriolis2
+
+See [[HDL_workflow/coriolis2]] page, for those people doing layout work.
+
+## Chips4Makers JTAG
+
+As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written. The Libre-SOC version includes DMI (Debug Memory Interface):
+
+ git clone https://git.libre-soc.org/c4m-jtag.git
+
+Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use.
+
+We added a DMI to JTAG bridge in LibreSOC which is directly connected to the core, to access registers and to be able to start and stop the core and change the PC. In combination with the JTAG Wishbone interface the test ASIC can have a bootloader uploaded directly into onboard SRAM and execution begun.