VCD reader support by using external tool

[yosys.git] / README.md

diff --git a/README.md b/README.md
index 0a81d8bb957898b2c5c0496c53277f2f4ab8778f..0232a5ed0e49becef721819b567651c4fdb5c612 100644 (file)
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
 ```
 yosys -- Yosys Open SYnthesis Suite
 

-Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>
+Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>

 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above


@@ -38,13 +38,13 @@ Web Site and Other Resources
 ============================
 
 More information and documentation can be found on the Yosys web site:
 ============================
 
 More information and documentation can be found on the Yosys web site:

-- http://www.clifford.at/yosys/
+- https://yosyshq.net/yosys/

 
 The "Documentation" page on the web site contains links to more resources,
 including a manual that even describes some of the Yosys internals:
 
 The "Documentation" page on the web site contains links to more resources,
 including a manual that even describes some of the Yosys internals:

-- http://www.clifford.at/yosys/documentation.html
+- https://yosyshq.net/yosys/documentation.html

 
 

-The file `CodingReadme` in this directory contains additional information
+The directory `guidelines` contains additional information

 for people interested in using the Yosys C++ APIs.
 
 Users interested in formal verification might want to use the formal verification
 for people interested in using the Yosys C++ APIs.
 
 Users interested in formal verification might want to use the formal verification


@@ -53,8 +53,23 @@ front-end for Yosys, SymbiYosys:
 - https://github.com/YosysHQ/SymbiYosys
 
 
 - https://github.com/YosysHQ/SymbiYosys
 
 

-Setup
-======
+Installation
+============
+
+Yosys is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.
+
+* [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link
+* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
+* Follow the [Install Instructions on GitHub](https://github.com/YosysHQ/oss-cad-suite-build#installation)
+
+Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!
+
+For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
+
+Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!
+
+Building from Source
+====================

 
 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
 
 You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.


@@ -90,10 +105,6 @@ For Cygwin use the following command to install all prerequisites, or select the
 
        setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
 
 
        setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel
 

-There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
-as a source distribution for Visual Studio. Visit the Yosys download page for
-more information: http://www.clifford.at/yosys/download.html
-

 To configure the build system to use a specific compiler, use one of
 
        $ make config-clang
 To configure the build system to use a specific compiler, use one of
 
        $ make config-clang


@@ -118,6 +129,13 @@ Tests are located in the tests subdirectory and can be executed using the test t
 
        $ make test
 
 
        $ make test
 

+To use a separate (out-of-tree) build directory, provide a path to the Makefile.
+
+       $ mkdir build; cd build
+       $ make -f ../Makefile
+
+Out-of-tree builds require a clean source tree.
+

 Getting Started
 ===============
 
 Getting Started
 ===============
 


@@ -274,6 +292,9 @@ Verilog Attributes and non-standard features
   temporary variable within an always block. This is mostly used internally
   by Yosys to synthesize Verilog functions and access arrays.
 
   temporary variable within an always block. This is mostly used internally
   by Yosys to synthesize Verilog functions and access arrays.
 

+- The ``nowrshmsk`` attribute on a register prohibits the generation of
+  shift-and-mask type circuits for writing to bit slices of that register.
+

 - The ``onehot`` attribute on wires mark them as one-hot state register. This
   is used for example for memory port sharing and set by the fsm_map pass.
 
 - The ``onehot`` attribute on wires mark them as one-hot state register. This
   is used for example for memory port sharing and set by the fsm_map pass.
 


@@ -299,7 +320,9 @@ Verilog Attributes and non-standard features
   that have ports with a width that depends on a parameter.
 
 - The ``hdlname`` attribute is used by some passes to document the original
   that have ports with a width that depends on a parameter.
 
 - The ``hdlname`` attribute is used by some passes to document the original

-  (HDL) name of a module when renaming a module.
+  (HDL) name of a module when renaming a module. It should contain a single
+  name, or, when describing a hierarchical name in a flattened design, multiple
+  names separated by a single space character.

 
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
 
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that


@@ -388,7 +411,7 @@ Verilog Attributes and non-standard features
 
 - The cell attribute ``wildcard_port_conns`` represents wildcard port
   connections (SystemVerilog ``.*``). These are resolved to concrete
 
 - The cell attribute ``wildcard_port_conns`` represents wildcard port
   connections (SystemVerilog ``.*``). These are resolved to concrete

-  connections to matching wires in ``hierarchy``.  
+  connections to matching wires in ``hierarchy``.

 
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
 
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes


@@ -477,6 +500,11 @@ Verilog Attributes and non-standard features
   for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
   enable this functionality. (By default these blocks are ignored.)
 
   for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
   enable this functionality. (By default these blocks are ignored.)
 

+- The ``reprocess_after`` internal attribute is used by the Verilog frontend to
+  mark cells with bindings which might depend on the specified instantiated
+  module. Modules with such cells will be reprocessed during the ``hierarchy``
+  pass once the referenced module definition(s) become available.
+

 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================


@@ -546,6 +574,8 @@ from SystemVerilog:
 - enums are supported (including inside packages)
        - but are currently not strongly typed
 
 - enums are supported (including inside packages)
        - but are currently not strongly typed
 

+- packed structs and unions are supported.
+

 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.
 
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.
 


@@ -554,7 +584,7 @@ Building the documentation
 ==========================
 
 Note that there is no need to build the manual if you just want to read it.
 ==========================
 
 Note that there is no need to build the manual if you just want to read it.

-Simply download the PDF from http://www.clifford.at/yosys/documentation.html
+Simply download the PDF from https://yosyshq.net/yosys/documentation.html

 instead.
 
 On Ubuntu, texlive needs these packages to be able to build the manual:
 instead.
 
 On Ubuntu, texlive needs these packages to be able to build the manual: