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Bump version
[yosys.git]
/
README.md
diff --git
a/README.md
b/README.md
index c17c0c3b1b1fab07b7b8bb2570ce4fcd7c44bf15..203a292d1b903588863d79dc127eac8415ca5ab8 100644
(file)
--- a/
README.md
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README.md
@@
-309,7
+309,9
@@
Verilog Attributes and non-standard features
that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
- (HDL) name of a module when renaming a module.
+ (HDL) name of a module when renaming a module. It should contain a single
+ name, or, when describing a hierarchical name in a flattened design, multiple
+ names separated by a single space character.
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
@@
-556,6
+558,8
@@
from SystemVerilog:
- enums are supported (including inside packages)
- but are currently not strongly typed
- enums are supported (including inside packages)
- but are currently not strongly typed
+- packed structs and unions are supported.
+
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.