-Throughout this Grant Proposal, you will note that we are making significant use of ideas from the early days of Computing. Due to the limitations of physical technology at that time, these ideas were categorised into "technology that was beyond delivery". Industry-standard computing from then to today missed many of those opportunities and has consequently ploughed narrow "technological ruts" in an incremental fashion that has detrimentally impacted and constrained all world-wide Computing end-users as a result. Modern hardware technology performance is now allowing us to revisit the best of the "Sea of ideas" from the history of the past 60 years of computing. Our Grant Application is therefore based on firm, practical proven foundations, backed up by a real-world customer requirement: Advanced high-accuracy GPS Sensor-Fusion, to prove the core's capabilities and energy efficiency.
-
-
-We have chosen to evolve core technology to develop a Next-Generation Supercomputer-scale Microprocessor family based on an existing 2-decades-proven base (the Power ISA), with Advanced Cray-style Vectors, providing energy-efficient advanced computational power by a unique methodology not currently being achieved by any current general-purpose computing device. We have been working on this strategy for over three years and our grant application is now evolutionary but was revolutionary.
-
-
-Libre-SOC has, for over three years, been backed by EU Funding through NLnet and now NGI POINTER, and at the core of our work we have been developing a novel Draft Vector ISA Extension to the OpenPOWER ISA, called SVP64. https://libre-soc.org/openpower/sv/svp64/ and an enhanced processor core architecture on which it will run.
-
-
-As an aside we must acknowledge the research work of IBM labs who designed and then Open-Licensed their Power ISA: the foundation on which we have been building. Standing on the shoulders of greatness is never a bad place to start.
-
-
-SVP64 contains features and capabilities never seen in any Instruction Set Architecture (ISA) of the past sixty years. With NLnet's help we have TRL (3) implementations and simulations demonstrating a 75% reduction in the program size of core algorithms for Video and Audio DSP Processing (FFT, DCT, Matrix Multiply), and these still need optimized, which if successfully expanded to general-purpose algorithms would result in huge power savings if deployed in mass-volume end-user products.
-
-
-Why we are leveraging the Power ISA as the fundamental basis instead of "completely novel non-standard computing architecture" requires some explanation, best illustrated by reference to other historic high capability designs. Aspex Microelectronics ASP was a 4096-wide SIMD Array of 2-bit processors. It could be programmed at a rate of one instruction per 5-10 days. Elixent also had a similar 2D Grid Array of 4-bit processors. Both were ultra-power-efficient (2 orders of magnitude for certain specialist tasks) but were impossible to program even for the best programming minds and required critical assistance from a severely limited pool of specialists for best exploitation. The Industry-standard rate for general-purpose High-Level programming (C, C++) is around 150 lines of code per day, not 5-10 days per line of assembler. We seek to deliver a much more accessible "general-purpose" Microprocessor that contains Supercomputing elements and consequently stands a much more realistic chance of general world-wide adoption (including Europe).
-
-
-An additional insight: OpenRISC 1200 took 12 years to reach maturity. The team developed the entire processor architecture, low-level software and compiler technology, entirely from scratch. We considered this approach and, due to the long timescales, rejected it, choosing instead to leverage and be compatible with a pre-existing Open ISA: OpenPOWER. We also considered RISC-V however it turns out to be too simplistic (https://news.ycombinator.com/item?id=24459041) and it is far too late to retrospectively add Supercomputer-grade power-efficient functionality to its design or instruction set. With the IBM-inspired Power ISA already being a Supercomputer-grade ISA, it is a natural fit for an energy-efficient Cray-style Vector upgrade, and comes with 25 years of pre-existing software, libraries, compilers and customers. By being backwards-compatible with the existing Power ISA 3.0 (which is now an Open ISA managed by the OpenPOWER Foundation), European businesses will benefit from that pre-existing decades-established stability and pedigree.
-
-
-As hinted at, above: Great hardware is nothing without the corresponding compiler technology and support libraries. Consequently we need to engage with Compiler Service Companies (Embecosm Gmbh, Vrull.eu) to evaluate the feasibility of adding Vectorisation support to gcc, llvm and low-level standard libraries. Whilst Libre-SOC has already demonstrated TRL (3) successful assembly-level SVP64 algorithms (MP3 CODEC in particular), assembler is far too low-level for general-purpose compute. C, C++ and other programming language support is required to be evaluated and developed. Also given that the Libre-SOC Core is being long-term designed for energy-efficient 3D GPU and Video Processing workloads, two 3D Vulkan Drivers (Kazan and MESA3D) need to be taken beyond proof-of-concept (TRL 2/3).
-
-
-We consider it strategically critical to develop processors in an entirely transparent fashion. The current Silicon Industry chooses secrecy to mask technology shortcuts and restrictive cross licencing, which inevitably and systematically fails to provide trustable hardware: Intel's Management Engine; Qualcomm making 40% of the world's smartphones vulnerable to hacking; Apple drive-by Zero-day Wireless exploits; Super-Micro being delisted from NASDAQ for failing to be able to prove the provenance of all hardware and software components. We consider Libre / Open Hardware ASICs and the full Libre/Open VLSI toolchain itself to be fundamental to end-user trust and security as well as Digital Sovereignty.
-
-
-In addition to this, Libre-SOC has already been developing Mathematical Formal Correctness Proofs for the HDL of its early prototype designs, which, in combination with unrestricted access to the HDL Source Code, allow third parties including customers to perform their own verification of the ASIC's purpose (as opposed to the customer having to trust a manufacture that inherently has a direct conflict-of-interest in the form of its Shareholders and profits). Furthermore, we aim to experiment with built-in "tamper-checking" circuits that, on running a test programme on our evaluation test bed, will provide an Electro-Magnetic "signature". By publishing this "signature" and the test programs, customers can verify that their purchased ASICs have the same EMF "signature" and can detect immediately if the ASIC has been tampered with. In addition we will continue existing (TRL 2) research into Hardware-level Speculative Execution mitigation techniques. We feel that the full combination of these objectives meets the Hardware Security requirements of this Call.
-
-
-This strategy does not end with just the HDL: thanks (again) to NLnet we have been collaborating already with Chips4Makers, LIP6 and CNRS (all funded by EU Grants), to advance the state-of-the-art for European VLSI Tool Technology, which is important to European Silicon Sovereignty.
+Throughout this Grant Proposal, you will note that we are making
+significant use of ideas from the early days of Computing. Due to
+the limitations of physical technology at that time, these ideas were
+categorised into "technology that was beyond delivery". Industry-standard
+computing from then to today missed many of those opportunities and
+has consequently ploughed narrow "technological ruts" in an incremental
+fashion that has detrimentally impacted and constrained all world-wide
+Computing end-users as a result. Modern hardware technology performance
+is now allowing us to revisit the best of the "Sea of ideas" from the
+history of the past 60 years of computing. Our Grant Application is
+therefore based on firm, practical proven foundations, backed up by a
+real-world customer requirement: Advanced high-accuracy GPS Sensor-Fusion,
+to prove the core's capabilities and energy efficiency.
+
+
+We have chosen to evolve core technology to develop a Next-Generation
+Supercomputer-scale Microprocessor family based on an existing
+2-decades-proven base (the Power ISA), with Advanced Cray-style Vectors,
+providing energy-efficient advanced computational power by a unique
+methodology not currently being achieved by any current general-purpose
+computing device. We have been working on this strategy for over three
+years and our grant application is now evolutionary but was revolutionary.
+
+
+Libre-SOC has, for over three years, been backed by EU Funding through
+NLnet and now NGI POINTER, and at the core of our work we have been
+developing a novel Draft Vector ISA Extension to the OpenPOWER ISA,
+called SVP64. https://libre-soc.org/openpower/sv/svp64/ and an enhanced
+processor core architecture on which it will run.
+
+
+As an aside we must acknowledge the research work of IBM labs who designed
+and then Open-Licensed their Power ISA: the foundation on which we have
+been building. Standing on the shoulders of greatness is never a bad
+place to start.
+
+
+SVP64 contains features and capabilities never seen in any Instruction
+Set Architecture (ISA) of the past sixty years. With NLnet's help we have
+TRL (3) implementations and simulations demonstrating a 75% reduction in
+the program size of core algorithms for Video and Audio DSP Processing
+(FFT, DCT, Matrix Multiply), and these still have room for optimisation,
+which if
+successfully expanded to general-purpose algorithms would result in huge
+power savings if deployed in mass-volume end-user products.
+
+
+Why we are leveraging the Power ISA as the fundamental basis instead of
+"completely novel non-standard computing architecture" requires some
+explanation, best illustrated by reference to other historic high
+capability designs. Aspex Microelectronics ASP was a 4096-wide SIMD
+Array of 2-bit processors. It could be programmed at a rate of one
+instruction per 5-10 days. Elixent also had a similar 2D Grid Array of
+4-bit processors. Both were ultra-power-efficient (2 orders of magnitude
+for certain specialist tasks) but were impossible to program even for the
+best programming minds and required critical assistance from a severely
+limited pool of specialists for best exploitation. The Industry-standard
+rate for general-purpose High-Level programming (C, C++) is around 150
+lines of code per day, not 5-10 days per line of assembler. We seek to
+deliver a much more accessible "general-purpose" Microprocessor that
+contains Supercomputing elements and consequently stands a much more
+realistic chance of general world-wide adoption (including Europe).
+
+
+An additional insight: OpenRISC 1200 took 12 years to reach maturity.
+The team developed the entire processor architecture, low-level software
+and compiler technology, entirely from scratch. We considered this
+approach and, due to the long timescales, rejected it, choosing
+instead to leverage and be compatible with a pre-existing Open ISA:
+OpenPOWER. We also considered RISC-V however it turns out to be too
+simplistic (https://news.ycombinator.com/item?id=24459041) and it is
+far too late to retrospectively add Supercomputer-grade power-efficient
+functionality to its design or instruction set. With the IBM-inspired
+Power ISA already being a Supercomputer-grade ISA, it is a natural fit for
+an energy-efficient Cray-style Vector upgrade, and comes with 25 years
+of pre-existing software, libraries, compilers and customers. By being
+backwards-compatible with the existing Power ISA 3.0 (which is now an
+Open ISA managed by the OpenPOWER Foundation), European businesses will
+benefit from that pre-existing decades-established stability and pedigree.
+
+
+As hinted at, above: Great hardware is nothing without the corresponding
+compiler technology and support libraries. Consequently we need to engage
+with Compiler Service Companies (Embecosm Gmbh, Vrull.eu) to evaluate the
+feasibility of adding Vectorisation support to gcc, llvm and low-level
+standard libraries. Whilst Libre-SOC has already demonstrated TRL (3)
+successful assembly-level SVP64 algorithms (MP3 CODEC in particular),
+assembler is far too low-level for general-purpose compute. C, C++
+and other programming language support is required to be evaluated
+and developed. Also given that the Libre-SOC Core is being long-term
+designed for energy-efficient 3D GPU and Video Processing workloads,
+two 3D Vulkan Drivers (Kazan and MESA3D) need to be taken beyond
+proof-of-concept (TRL 2/3).
+
+
+We consider it strategically critical to develop processors in an entirely
+transparent fashion. The current Silicon Industry chooses secrecy to mask
+technology shortcuts and restrictive cross licencing, which inevitably and
+systematically fails to provide trustable hardware: Intel's Management
+Engine; Qualcomm making 40% of the world's smartphones vulnerable to
+hacking; Apple drive-by Zero-day Wireless exploits; Super-Micro being
+delisted from NASDAQ for failing to be able to prove the provenance of
+all hardware and software components. We consider Libre / Open Hardware
+ASICs and the full Libre/Open VLSI toolchain itself to be fundamental
+to end-user trust and security as well as Digital Sovereignty.
+
+
+In addition to this, Libre-SOC has already been developing Mathematical
+Formal Correctness Proofs for the HDL of its early prototype designs,
+which, in combination with unrestricted access to the HDL Source Code,
+allow third parties including customers to perform their own verification
+of the ASIC's purpose (as opposed to the customer having to trust a
+manufacture that inherently has a direct conflict-of-interest in the form
+of its Shareholders and profits). Furthermore, we aim to experiment with
+built-in "tamper-checking" circuits that, on running a test programme on
+our evaluation test bed, will provide an Electro-Magnetic "signature".
+By publishing this "signature" and the test programs, customers can
+verify that their purchased ASICs have the same EMF "signature" and can
+detect immediately if the ASIC has been tampered with. In addition we
+will continue existing (TRL 2) research into Hardware-level Speculative
+Execution mitigation techniques. We feel that the full combination of
+these objectives meets the Hardware Security requirements of this Call.
+
+
+This strategy does not end with just the HDL: thanks (again) to NLnet
+we have been collaborating already with Chips4Makers, LIP6 and CNRS
+(all funded by EU Grants), to advance the state-of-the-art for European
+VLSI Tool Technology, which is important to European Silicon Sovereignty.