+
+## [[Alain Williams|addw]]
+
+Alain's website: <http://phcomp.co.uk>
+
+## [[Cesar Strauss|Cesar_Strauss]]
+
+* Experience: Data acquisition and control for scientific instruments
+* Programming of microcontrolers and FPGAs
+* Digital circuit design
+* Availability: Outside normal working hours.
+
+## [[Cole Poirier|cole]]
+
+* Trying to learn and organize stuff
+* GitHub: [[https://github.com/colepoirier]]
+* Availability: full-time
+
+## [[Sanjay A Menon|Sanjay]]
+
+* Skills: Verilog, C/C++, Python, TCL & PERL
+* Github Profile: [[https://github.com/Sanjay-A-Menon]]
+* LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]]
+* Availability: ~6hrs/week
+
+## [[Samuel A Falvo II]]
+
+* Experience in amateur HDL projects (Kestrel-3 homebrew computer
+ concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
+ design. Extensive experience with test-driven development, Python,
+ assembly language for a wide variety of CPUs including RISC-V, and Forth.
+ Very comfortable with nMigen, but still learning things.
+* Interests: Forth, Common Lisp, Scheme, assembly language,
+ {Astro|Semiconductor-}physics, astronomy, martial arts, furry (character: black dragon; name: "Vertigo").
+* Websites:
+ - https://hackaday.io/project/170581-vdc-ii ,
+ - https://kestrelcomputer.github.io/kestrel/ ,
+ - http://chiselapp.com/user/kc5tja/repository/kestrel-3/index
+* Public Repositories:
+ - https://github.com/sam-falvo ,
+ - https://github.com/kestrelcomputer
+* Availability: approximately 20 hrs/wk, circumstances permitting.
+
+## [[Alex Oliva|lxo]]
+
+* Experience: GCC, binutils, glibc, GNU autotools, Free Software activism.
+* website: [[https://www.fsfla.org/~lxoliva/]]
+* Availability: 10+hrs/week