- TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
- dict<SigBit, pool<IdString>> bit_drivers, bit_users;
-
- for (auto cell : module->selected_cells()) {
- RTLIL::Module* inst_module = module->design->module(cell->type);
- if (!inst_module || !inst_module->attributes.count("\\abc_box_id"))
- continue;
- toposort.node(cell->name);
- for (const auto &conn : cell->connections()) {
- if (cell->input(conn.first)) {
- // Ignore inout for the sake of topographical ordering
- if (cell->output(conn.first)) continue;
- for (auto bit : topomap(conn.second))
- if (bit.wire)
- bit_users[bit].insert(cell->name);
- }
-
- if (cell->output(conn.first)) {
- RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
- log_assert(inst_module_port);
- //if (inst_module_port->attributes.count("\\abc_flop_q"))
- // continue;
- for (auto bit : topomap(conn.second))
- bit_drivers[bit].insert(cell->name);
- }
- }
- }
-