- if (symbols_mode)
- {
- dict<string, vector<string>> symbols;
-
- bool output_seen = false;
- for (auto wire : module->wires())
- {
- //if (wire->name[0] == '$')
- // continue;
-
- SigSpec sig = sigmap(wire);
-
- for (int i = 0; i < GetSize(wire); i++)
- {
- RTLIL::SigBit b(wire, i);
- if (input_bits.count(b)) {
- int a = aig_map.at(sig[i]);
- log_assert((a & 1) == 0);
- if (GetSize(wire) != 1)
- symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
- else
- symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
- }
-
- if (output_bits.count(b)) {
- int o = ordered_outputs.at(b);
- output_seen = !miter_mode;
- if (GetSize(wire) != 1)
- symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
- else
- symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
- }
-
- //if (init_inputs.count(sig[i])) {
- // int a = init_inputs.at(sig[i]);
- // log_assert((a & 1) == 0);
- // if (GetSize(wire) != 1)
- // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
- // else
- // symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
- //}
-
- if (ordered_latches.count(sig[i])) {
- int l = ordered_latches.at(sig[i]);
- const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
- if (GetSize(wire) != 1)
- symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
- else
- symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
- }
- }
- }
-
- if (omode && !output_seen)
- symbols["o0"].push_back("__dummy_o__");
-
- symbols.sort();
-
- for (auto &sym : symbols) {
- f << sym.first;
- std::sort(sym.second.begin(), sym.second.end());
- for (auto &s : sym.second)
- f << " " << s;
- f << std::endl;
- }
- }
-