+ if options.checker:
+ system.cpu[i].addCheckerCpu()
+
+ system.cpu[i].createThreads()
+
+if options.ruby:
+ if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU":
+ print >> sys.stderr, "Ruby does not work with atomic cpu!!"
+ sys.exit(1)
+
+ Ruby.create_system(options, False, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ports))
+
+ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
+ for i in xrange(np):
+ ruby_port = system.ruby._cpu_ports[i]
+
+ # Create the interrupt controller and connect its ports to Ruby
+ # Note that the interrupt controller is always present but only
+ # in x86 does it have message ports that need to be connected
+ system.cpu[i].createInterruptController()
+
+ # Connect the cpu's cache ports to Ruby
+ system.cpu[i].icache_port = ruby_port.slave
+ system.cpu[i].dcache_port = ruby_port.slave
+ if buildEnv['TARGET_ISA'] == 'x86':
+ system.cpu[i].interrupts[0].pio = ruby_port.master
+ system.cpu[i].interrupts[0].int_master = ruby_port.slave
+ system.cpu[i].interrupts[0].int_slave = ruby_port.master
+ system.cpu[i].itb.walker.port = ruby_port.slave
+ system.cpu[i].dtb.walker.port = ruby_port.slave
+else:
+ MemClass = Simulation.setMemClass(options)
+ system.membus = SystemXBar()
+ system.system_port = system.membus.slave
+ CacheConfig.config_cache(options, system)
+ MemConfig.config_mem(options, system)