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Hand merge
[gem5.git]
/
cpu
/
base_dyn_inst.hh
diff --git
a/cpu/base_dyn_inst.hh
b/cpu/base_dyn_inst.hh
index 7651b517e6d959b5cae5d83cf1ae1d79410ef02a..171721e61a6ce7c94b8938184a46d7f2566d6285 100644
(file)
--- a/
cpu/base_dyn_inst.hh
+++ b/
cpu/base_dyn_inst.hh
@@
-53,12
+53,12
@@
namespace Trace {
class InstRecord;
};
class InstRecord;
};
-class BaseInst
-{
-
}
;
+// Forward declaration.
+template <class blah>
+
class StaticInstPtr
;
template <class Impl>
template <class Impl>
-class BaseDynInst : public FastAlloc
+class BaseDynInst : public FastAlloc
, public RefCounted
{
public:
// Typedef for the CPU.
{
public:
// Typedef for the CPU.
@@
-74,7
+74,7
@@
class BaseDynInst : public FastAlloc
/// Logical register index type.
typedef typename ISA::RegIndex RegIndex;
/// Integer register index type.
/// Logical register index type.
typedef typename ISA::RegIndex RegIndex;
/// Integer register index type.
- typedef typename ISA::IntReg IntReg;
+ typedef typename ISA::IntReg
IntReg;
enum {
MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
enum {
MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
@@
-146,7
+146,10
@@
class BaseDynInst : public FastAlloc
bool threadsyncWait;
/** If the BTB missed. */
bool threadsyncWait;
/** If the BTB missed. */
- bool btbMissed;
+// bool btbMissed;
+
+ /** The global history of this instruction (branch). */
+// unsigned globalHistory;
/** The thread this instruction is from. */
short threadNumber;
/** The thread this instruction is from. */
short threadNumber;
@@
-212,7
+215,7
@@
class BaseDynInst : public FastAlloc
static int instcount;
/** Did this instruction do a spec write? */
static int instcount;
/** Did this instruction do a spec write? */
- bool specMemWrite;
+
//
bool specMemWrite;
private:
/** Physical register index of the destination registers of this
private:
/** Physical register index of the destination registers of this
@@
-287,15
+290,22
@@
class BaseDynInst : public FastAlloc
/** Returns whether the instruction was predicted taken or not. */
bool predTaken() {
/** Returns whether the instruction was predicted taken or not. */
bool predTaken() {
-// DPRINTF(FullCPU, "PC: %08p\n", PC);
-// DPRINTF(FullCPU, "predPC: %08p\n", predPC);
-
return( predPC != (PC + sizeof(MachInst) ) );
}
/** Returns whether the instruction mispredicted. */
bool mispredicted() { return (predPC != nextPC); }
return( predPC != (PC + sizeof(MachInst) ) );
}
/** Returns whether the instruction mispredicted. */
bool mispredicted() { return (predPC != nextPC); }
+/*
+ unsigned readGlobalHist() {
+ return globalHistory;
+ }
+
+ void setGlobalHist(unsigned history) {
+ globalHistory = history;
+ }
+*/
+
//
// Instruction types. Forward checks to StaticInst object.
//
//
// Instruction types. Forward checks to StaticInst object.
//
@@
-430,6
+440,9
@@
class BaseDynInst : public FastAlloc
/** Sets this instruction as ready to commit. */
void setCanCommit() { canCommit = true; }
/** Sets this instruction as ready to commit. */
void setCanCommit() { canCommit = true; }
+ /** Clears this instruction as being ready to commit. */
+ void clearCanCommit() { canCommit = false; }
+
/** Returns whether or not this instruction is ready to commit. */
bool readyToCommit() const { return canCommit; }
/** Returns whether or not this instruction is ready to commit. */
bool readyToCommit() const { return canCommit; }
@@
-449,7
+462,7
@@
class BaseDynInst : public FastAlloc
OpClass opClass() const { return staticInst->opClass(); }
/** Returns whether or not the BTB missed. */
OpClass opClass() const { return staticInst->opClass(); }
/** Returns whether or not the BTB missed. */
- bool btbMiss() const { return btbMissed; }
+
//
bool btbMiss() const { return btbMissed; }
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
@@
-576,8
+589,8
@@
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
storeSize = sizeof(T);
storeData = data;
storeSize = sizeof(T);
storeData = data;
- if (specMode)
-
specMemWrite = true;
+
//
if (specMode)
+
//
specMemWrite = true;
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);