- // Do data first to match tracing with FullCPU dumps
-
- while (nextDataReq && (dataReqs < dcachePorts) &&
- curTick >= nextDataCycle) {
- assert(nextDataReq->thread_num < 4 && "Not enough threads");
- if (dcacheInterface->isBlocked())
- break;
-
- ++dataReqs;
- nextDataReq->time = curTick;
- nextDataReq->completionEvent =
- new TraceCompleteEvent(nextDataReq, this);
- dcacheInterface->access(nextDataReq);
- nextDataCycle = dataTrace->getNextReq(nextDataReq);
- }
-
- while (nextInstReq && (instReqs < icachePorts) &&
- curTick >= nextInstCycle) {
- assert(nextInstReq->thread_num < 4 && "Not enough threads");
- if (icacheInterface->isBlocked())
- break;
-
- nextInstReq->time = curTick;
- if (nextInstReq->cmd == Squash) {
- icacheInterface->squash(nextInstReq->asid);
+ while (nextReq && curTick >= nextCycle) {
+ assert(nextReq->thread_num < 4 && "Not enough threads");
+ if (nextReq->isInstRead() && icacheInterface) {
+ if (icacheInterface->isBlocked())
+ break;
+
+ nextReq->time = curTick;
+ if (nextReq->cmd == Squash) {
+ icacheInterface->squash(nextReq->asid);
+ } else {
+ ++instReqs;
+ if (icacheInterface->doEvents()) {
+ nextReq->completionEvent =
+ new TraceCompleteEvent(nextReq, this);
+ icacheInterface->access(nextReq);
+ } else {
+ icacheInterface->access(nextReq);
+ completeRequest(nextReq);
+ }
+ }