self.clk = ClockSignal()
self.reset = ResetSignal()
#output [31:2] memory_interface_fetch_address,
self.clk = ClockSignal()
self.reset = ResetSignal()
#output [31:2] memory_interface_fetch_address,
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
delayed_instruction_valid = Signal(reset=0)
self.sync += delayed_instruction.eq(self.output_instruction)
delayed_instruction_valid = Signal(reset=0)
self.sync += delayed_instruction.eq(self.output_instruction)
self.comb += If(delayed_instruction_valid,
self.output_instruction.eq(delayed_instruction)
self.comb += If(delayed_instruction_valid,
self.output_instruction.eq(delayed_instruction)
}
fc[fetch_action_default] = fc[fetch_action_ack_trap]
fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
}
fc[fetch_action_default] = fc[fetch_action_ack_trap]
fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
example.memory_interface_fetch_data,
example.memory_interface_fetch_valid,
example.fetch_action,
example.memory_interface_fetch_data,
example.memory_interface_fetch_valid,
example.fetch_action,