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Improve architectural compliance of mfspr and mtspr
[microwatt.git]
/
dcache_tb.vhdl
diff --git
a/dcache_tb.vhdl
b/dcache_tb.vhdl
index 437fd7d3312ae9691ce2a1acd00c94fd4b87af9f..bd8341a083df1e61d8a02166a5f2ea1ee86f2dac 100644
(file)
--- a/
dcache_tb.vhdl
+++ b/
dcache_tb.vhdl
@@
-13,7
+13,7
@@
architecture behave of dcache_tb is
signal rst : std_ulogic;
signal d_in : Loadstore1ToDcacheType;
signal rst : std_ulogic;
signal d_in : Loadstore1ToDcacheType;
- signal d_out : DcacheTo
Writeback
Type;
+ signal d_out : DcacheTo
Loadstore1
Type;
signal wb_bram_in : wishbone_master_out;
signal wb_bram_out : wishbone_slave_out;
signal wb_bram_in : wishbone_master_out;
signal wb_bram_out : wishbone_slave_out;
@@
-71,12
+71,6
@@
begin
d_in.nc <= '0';
d_in.addr <= (others => '0');
d_in.data <= (others => '0');
d_in.nc <= '0';
d_in.addr <= (others => '0');
d_in.data <= (others => '0');
- d_in.write_reg <= (others => '0');
- d_in.length <= (others => '0');
- d_in.byte_reverse <= '0';
- d_in.sign_extend <= '0';
- d_in.update <= '0';
- d_in.update_reg <= (others => '0');
wait for 4*clk_period;
wait until rising_edge(clk);
wait for 4*clk_period;
wait until rising_edge(clk);
@@
-89,11
+83,10
@@
begin
wait until rising_edge(clk);
d_in.valid <= '0';
wait until rising_edge(clk);
d_in.valid <= '0';
- wait until rising_edge(clk) and d_out.write_enable = '1';
- assert d_out.valid = '1';
- assert d_out.write_data = x"0000000100000000"
+ wait until rising_edge(clk) and d_out.valid = '1';
+ assert d_out.data = x"0000000100000000"
report "data @" & to_hstring(d_in.addr) &
report "data @" & to_hstring(d_in.addr) &
- "=" & to_hstring(d_out.
write_
data) &
+ "=" & to_hstring(d_out.data) &
" expected 0000000100000000"
severity failure;
-- wait for clk_period;
" expected 0000000100000000"
severity failure;
-- wait for clk_period;
@@
-106,11
+99,10
@@
begin
wait until rising_edge(clk);
d_in.valid <= '0';
wait until rising_edge(clk);
d_in.valid <= '0';
- wait until rising_edge(clk) and d_out.write_enable = '1';
- assert d_out.valid = '1';
- assert d_out.write_data = x"0000000D0000000C"
+ wait until rising_edge(clk) and d_out.valid = '1';
+ assert d_out.data = x"0000000D0000000C"
report "data @" & to_hstring(d_in.addr) &
report "data @" & to_hstring(d_in.addr) &
- "=" & to_hstring(d_out.
write_
data) &
+ "=" & to_hstring(d_out.data) &
" expected 0000000D0000000C"
severity failure;
" expected 0000000D0000000C"
severity failure;
@@
-121,11
+113,10
@@
begin
d_in.valid <= '1';
wait until rising_edge(clk);
d_in.valid <= '0';
d_in.valid <= '1';
wait until rising_edge(clk);
d_in.valid <= '0';
- wait until rising_edge(clk) and d_out.write_enable = '1';
- assert d_out.valid = '1';
- assert d_out.write_data = x"0000004100000040"
+ wait until rising_edge(clk) and d_out.valid = '1';
+ assert d_out.data = x"0000004100000040"
report "data @" & to_hstring(d_in.addr) &
report "data @" & to_hstring(d_in.addr) &
- "=" & to_hstring(d_out.
write_
data) &
+ "=" & to_hstring(d_out.data) &
" expected 0000004100000040"
severity failure;
" expected 0000004100000040"
severity failure;