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better debugging of DMA operations
[gem5.git]
/
dev
/
pciconfigall.cc
diff --git
a/dev/pciconfigall.cc
b/dev/pciconfigall.cc
index 63943c7be17f55fd2a16ee2f3e0d869bb8658d14..740a9b4acd7685070107806ed27c877d82f461d4 100644
(file)
--- a/
dev/pciconfigall.cc
+++ b/
dev/pciconfigall.cc
@@
-1,5
+1,5
@@
/*
/*
- * Copyright (c) 200
3
The Regents of The University of Michigan
+ * Copyright (c) 200
4
The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@
-35,26
+35,29
@@
#include <vector>
#include "base/trace.hh"
#include <vector>
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "dev/scsi_ctrl.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
-#include "dev/tsunamireg.h"
-#include "dev/tsunami.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
-P
CIConfigAll::PCIConfigAll(const string &name, Tsunami *t, Addr a
,
-
MemoryController *mmu
)
- :
FunctionalMemory(name), addr(a), tsunami(t
)
+P
ciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu
,
+
HierParams *hier, Bus *bus, Tick pio_latency
)
+ :
PioDevice(name), addr(a
)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
- // Put back pointer in tsunami
- tsunami->pciconfig = this;
+ if (bus) {
+ pioInterface = newPioInterface(name, hier, bus, this,
+ &PciConfigAll::cacheAccess);
+ pioInterface->addAddrRange(addr, addr + size - 1);
+ pioLatency = pio_latency * bus->clockRatio;
+ }
// Make all the pointers to devices null
for(int x=0; x < MAX_PCI_DEV; x++)
// Make all the pointers to devices null
for(int x=0; x < MAX_PCI_DEV; x++)
@@
-63,9
+66,9
@@
PCIConfigAll::PCIConfigAll(const string &name, Tsunami *t, Addr a,
}
Fault
}
Fault
-P
CI
ConfigAll::read(MemReqPtr &req, uint8_t *data)
+P
ci
ConfigAll::read(MemReqPtr &req, uint8_t *data)
{
{
- DPRINTF(P
CI
ConfigAll, "read va=%#x size=%d\n",
+ DPRINTF(P
ci
ConfigAll, "read va=%#x size=%d\n",
req->vaddr, req->size);
Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
req->vaddr, req->size);
Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
@@
-103,14
+106,14
@@
PCIConfigAll::read(MemReqPtr &req, uint8_t *data)
}
}
}
}
- DPRINTFN("
Tsunami
PCI Configspace ERROR: read daddr=%#x size=%d\n",
+ DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
return No_Fault;
}
Fault
daddr, req->size);
return No_Fault;
}
Fault
-P
CI
ConfigAll::write(MemReqPtr &req, const uint8_t *data)
+P
ci
ConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
{
Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
@@
-142,7
+145,7
@@
PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
}
}
}
}
- DPRINTF(P
CI
ConfigAll, "write - va=%#x size=%d data=%#x\n",
+ DPRINTF(P
ci
ConfigAll, "write - va=%#x size=%d data=%#x\n",
req->vaddr, req->size, word_value);
devices[device][func]->WriteConfig(reg, req->size, word_value);
req->vaddr, req->size, word_value);
devices[device][func]->WriteConfig(reg, req->size, word_value);
@@
-151,42
+154,61
@@
PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
}
void
}
void
-P
CI
ConfigAll::serialize(std::ostream &os)
+P
ci
ConfigAll::serialize(std::ostream &os)
{
{
- // code should be written
+ /*
+ * There is no state associated with this object that requires
+ * serialization. The only real state are the device pointers
+ * which are all setup by the constructor of the PciDev class
+ */
}
void
}
void
-PCIConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
+PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ /*
+ * There is no state associated with this object that requires
+ * serialization. The only real state are the device pointers
+ * which are all setup by the constructor of the PciDev class
+ */
+}
+
+Tick
+PciConfigAll::cacheAccess(MemReqPtr &req)
{
{
- //code should be written
+ return curTick + pioLatency;
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(P
CI
ConfigAll)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(P
ci
ConfigAll)
- SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
+ SimObjectParam<Bus*> io_bus;
+ Param<Tick> pio_latency;
+ SimObjectParam<HierParams *> hier;
-END_DECLARE_SIM_OBJECT_PARAMS(P
CI
ConfigAll)
+END_DECLARE_SIM_OBJECT_PARAMS(P
ci
ConfigAll)
-BEGIN_INIT_SIM_OBJECT_PARAMS(P
CI
ConfigAll)
+BEGIN_INIT_SIM_OBJECT_PARAMS(P
ci
ConfigAll)
- INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
- INIT_PARAM(mask, "Address Mask")
+ INIT_PARAM(mask, "Address Mask"),
+ INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
-END_INIT_SIM_OBJECT_PARAMS(P
CI
ConfigAll)
+END_INIT_SIM_OBJECT_PARAMS(P
ci
ConfigAll)
-CREATE_SIM_OBJECT(P
CI
ConfigAll)
+CREATE_SIM_OBJECT(P
ci
ConfigAll)
{
{
- return new PCIConfigAll(getInstanceName(), tsunami, addr, mmu);
+ return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
+ pio_latency);
}
}
-REGISTER_SIM_OBJECT("P
CIConfigAll", PCI
ConfigAll)
+REGISTER_SIM_OBJECT("P
ciConfigAll", Pci
ConfigAll)
#endif // DOXYGEN_SHOULD_SKIP_THIS
#endif // DOXYGEN_SHOULD_SKIP_THIS