- PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func);
-
- dev->config.hdr.vendor = VendorID;
- dev->config.hdr.device = DeviceID;
- dev->config.hdr.command = Command;
- dev->config.hdr.status = Status;
- dev->config.hdr.revision = Revision;
- dev->config.hdr.progIF = ProgIF;
- dev->config.hdr.subClassCode = SubClassCode;
- dev->config.hdr.classCode = ClassCode;
- dev->config.hdr.cacheLineSize = CacheLineSize;
- dev->config.hdr.latencyTimer = LatencyTimer;
- dev->config.hdr.headerType = HeaderType;
- dev->config.hdr.bist = BIST;
-
- dev->config.hdr.pci0.baseAddr0 = BAR0;
- dev->config.hdr.pci0.baseAddr1 = BAR1;
- dev->config.hdr.pci0.baseAddr2 = BAR2;
- dev->config.hdr.pci0.baseAddr3 = BAR3;
- dev->config.hdr.pci0.baseAddr4 = BAR4;
- dev->config.hdr.pci0.baseAddr5 = BAR5;
- dev->config.hdr.pci0.cardbusCIS = CardbusCIS;
- dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
- dev->config.hdr.pci0.subsystemID = SubsystemVendorID;
- dev->config.hdr.pci0.expansionROM = ExpansionROM;
- dev->config.hdr.pci0.interruptLine = InterruptLine;
- dev->config.hdr.pci0.interruptPin = InterruptPin;
- dev->config.hdr.pci0.minimumGrant = MinimumGrant;
- dev->config.hdr.pci0.maximumLatency = MaximumLatency;
-
- dev->BARSize[0] = BAR0Size;
- dev->BARSize[1] = BAR1Size;
- dev->BARSize[2] = BAR2Size;
- dev->BARSize[3] = BAR3Size;
- dev->BARSize[4] = BAR4Size;
- dev->BARSize[5] = BAR5Size;
-
- return dev;
+ PciConfigData *data = new PciConfigData(getInstanceName());
+
+ data->config.hdr.vendor = htoa(VendorID);
+ data->config.hdr.device = htoa(DeviceID);
+ data->config.hdr.command = htoa(Command);
+ data->config.hdr.status = htoa(Status);
+ data->config.hdr.revision = htoa(Revision);
+ data->config.hdr.progIF = htoa(ProgIF);
+ data->config.hdr.subClassCode = htoa(SubClassCode);
+ data->config.hdr.classCode = htoa(ClassCode);
+ data->config.hdr.cacheLineSize = htoa(CacheLineSize);
+ data->config.hdr.latencyTimer = htoa(LatencyTimer);
+ data->config.hdr.headerType = htoa(HeaderType);
+ data->config.hdr.bist = htoa(BIST);
+
+ data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
+ data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
+ data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
+ data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
+ data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
+ data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
+ data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
+ data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
+ data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
+ data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
+ data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
+ data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
+ data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
+ data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
+
+ data->BARSize[0] = BAR0Size;
+ data->BARSize[1] = BAR1Size;
+ data->BARSize[2] = BAR2Size;
+ data->BARSize[3] = BAR3Size;
+ data->BARSize[4] = BAR4Size;
+ data->BARSize[5] = BAR5Size;
+
+ return data;