- //If it is the seventh bit, clear the RTC interrupt
- if ((*(uint64_t*) data) & (1<<4)) {
- RTCInterrupting = false;
- tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
- DPRINTF(Tsunami, "clearing rtc interrupt\n");
- misc &= ~(1<<4);
- } else panic("TSDEV_CC_MISC write not implemented\n");
- return No_Fault;
+ //If it is the 4-7th bit, clear the RTC interrupt
+ uint64_t itintr;
+ if ((itintr = (*(uint64_t*) data) & (0xf<<4))) {
+ //Clear the bits in ITINTR
+ misc &= ~(itintr);
+ for (int i=0; i < size; i++) {
+ if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) {
+ tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
+ RTCInterrupting[i] = false;
+ DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
+ }
+ }
+ supportedWrite = true;
+ }
+ //If it is 12th-15th bit, IPI sent to Processor 1
+ uint64_t ipreq;
+ if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) {
+ //Set the bits in IPINTR
+ misc |= (ipreq >> 4);
+ for (int i=0; i < size; i++) {
+ if ((ipreq & (1 << (i + 12)))) {
+ if (!ipiInterrupting[i])
+ tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0);
+ ipiInterrupting[i]++;
+ DPRINTF(IPI, "send cpu=%d pending=%d from=%d\n", i,
+ ipiInterrupting[i], req->cpu_num);
+ }
+ }
+ supportedWrite = true;
+ }
+ //If it is bits 8-11, then clearing IPI's
+ uint64_t ipintr;
+ if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) {
+ //Clear the bits in IPINTR
+ misc &= ~(ipintr);
+ for (int i=0; i < size; i++) {
+ if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) {
+ if (!(--ipiInterrupting[i]))
+ tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0);
+ DPRINTF(IPI, "clearing cpu=%d pending=%d from=%d\n", i,
+ ipiInterrupting[i] + 1, req->cpu_num);
+ }
+ }
+ supportedWrite = true;
+ }
+
+ // ignore NXMs
+ if (*(uint64_t*)data & 0x10000000)
+ supportedWrite = true;
+
+ if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n");
+ return No_Fault;