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Better handling of latency/frequency parameter types
[gem5.git]
/
dev
/
tsunami_pchip.hh
diff --git
a/dev/tsunami_pchip.hh
b/dev/tsunami_pchip.hh
index f3c250d717f4cdf602e85c6a0a6e3702bc6ab7e2..f88098d58923eb4db9c190aef9d0a3b1e7a669ea 100644
(file)
--- a/
dev/tsunami_pchip.hh
+++ b/
dev/tsunami_pchip.hh
@@
-33,13
+33,14
@@
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
-#include "mem/functional_mem/functional_memory.hh"
#include "dev/tsunami.hh"
#include "dev/tsunami.hh"
+#include "base/range.hh"
+#include "dev/io_device.hh"
/*
* Tsunami PChip
*/
/*
* Tsunami PChip
*/
-class TsunamiPChip : public
FunctionalMemory
+class TsunamiPChip : public
PioDevice
{
private:
/** The base address of this device */
{
private:
/** The base address of this device */
@@
-75,9
+76,12
@@
class TsunamiPChip : public FunctionalMemory
* @param t a pointer to the tsunami device
* @param a the address which we respond to
* @param mmu the mmu we are to register with
* @param t a pointer to the tsunami device
* @param a the address which we respond to
* @param mmu the mmu we are to register with
+ * @param hier object to store parameters universal the device hierarchy
+ * @param bus The bus that this device is attached to
*/
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
*/
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
- MemoryController *mmu);
+ MemoryController *mmu, HierParams *hier, Bus *bus,
+ Tick pio_latency);
/**
* Translate a PCI bus address to a memory address for DMA.
/**
* Translate a PCI bus address to a memory address for DMA.
@@
-115,6
+119,13
@@
class TsunamiPChip : public FunctionalMemory
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
+ /**
+ * Return how long this access will take.
+ * @param req the memory request to calcuate
+ * @return Tick when the request is done
+ */
+ Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_PCHIP_HH__
};
#endif // __TSUNAMI_PCHIP_HH__