bug 1048, ls011: Remove inline import of PowerISA 3.0 ldst insn's

[libreriscv.git] / docs.mdwn

diff --git a/docs.mdwn b/docs.mdwn
index 485663c7e0efd00a164923bf00936e357cd4589f..18056542cac3ce42d96d8f435fe651e212b4c282 100644 (file)
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -3,7 +3,7 @@
 A draft version of the specification is available at
 <https://ftp.libre-soc.org/power-spec-draft.pdf>
 
 A draft version of the specification is available at
 <https://ftp.libre-soc.org/power-spec-draft.pdf>
 

-## Codebase Structure
+# Codebase Structure

 
 The SOC is partitioned into four repositories. The subrepositories are
 intended as general purpose standalone projects useful outside of LibreSOC. For example,
 
 The SOC is partitioned into four repositories. The subrepositories are
 intended as general purpose standalone projects useful outside of LibreSOC. For example,


@@ -13,14 +13,11 @@ construction of FSMs and arbitrary length pipelines.
 | Git Repo | Online docs   | Description   | Pypi    |
 |----------|---------------|---------------|--------
 | [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | TBD |
 | Git Repo | Online docs   | Description   | Pypi    |
 |----------|---------------|---------------|--------
 | [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | TBD |

-| [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | -- | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) |
-| [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | -- | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) |
+| [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | [ieee754fpu](https://docs.libre-soc.org/ieee754fpu/) | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) |
+| [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [nmutil](https://docs.libre-soc.org/nmutil/) | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) |

 | [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure |  [libresoc-openpower-isa](https://pypi.org/project/libresoc-openpower-isa/)  |
 
 | [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure |  [libresoc-openpower-isa](https://pypi.org/project/libresoc-openpower-isa/)  |
 

-
-Also see [[SOC Architecture|3d_gpu/architecture]]
-
-## Installing the Codebase
+# Installing the Codebase

 
 Installation is much easier when using the
 [install scripts](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD).
 
 Installation is much easier when using the
 [install scripts](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD).


@@ -33,31 +30,33 @@ The chroot is useful to ensure stability and repeatable builds: no
 errors or issues introduced by libraries being wrong versions.
 Also relevant is the [gdb gcc build](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=ppc64-gdb-gcc;hb=HEAD).
 
 errors or issues introduced by libraries being wrong versions.
 Also relevant is the [gdb gcc build](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=ppc64-gdb-gcc;hb=HEAD).
 

-    pip3 install virtualenv requests
-    mkdir ~/.virtualenvs && cd ~/.virtualenvs
-    python3 -m venv libresoc
-    source ~/.virtualenvs/libresoc/bin/activate
-    
-    cd ~; mkdir libresoc; cd libresoc
-    git clone https://git.libre-soc.org/git/nmutil.git
-    git clone https://git.libre-soc.org/git/openpower-isa.git
-    git clone https://git.libre-soc.org/git/c4m-jtag.git
-    git clone https://git.libre-soc.org/git/ieee754fpu.git
-    git clone https://git.libre-soc.org/git/soc.git
-    
-    cd nmutil; make develop; cd ..
-    cd openpower-isa; make develop; cd ..
-    cd c4m-jtag; make develop; cd ..
-    cd ieee754fpu; make develop; cd ..
-    cd soc; make gitupdate; make develop; cd ..
-    
-    python3 soc/src/soc/decoder/power_decoder.py
-    yosys -p "read_ilang decoder.il; show dec31" 
-
-## Gtkwave Tutorial
-
-[[docs/gtkwave_tutorial]]
-
-## Formal proof notes
-
-[[docs/notes_on_formal_proofs]]
+For a simple set of commands to follow, see [[HDL_workflow/devscripts]]. If
+you prefer to do a manual install and explicitly install dependencies
+yourself, in order to verify them, see [[HDL_workflow]]
+
+# Tutorials and documentation
+
+* [[SOC Architecture|3d_gpu/architecture]]
+* Gtkwave Tutorial [[docs/gtkwave_tutorial]]
+* Formal proof notes [[docs/notes_on_formal_proofs]]
+* Learning nmigen [[docs/learning_nmigen]]
+* Test API [[docs/testapi]]
+* Pinmux and JTAG Boundary Scan [[docs/pinmux]]
+* pypowersim python-based command-line simulator [[docs/pypowersim]]
+* First steps [[docs/firststeps]]
+* Adding an instruction [[docs/adding_instr]] - see also below
+
+# SVP64
+
+Currently in Draft form, [[openpower/sv/svp64]] is the basis of the
+Supercomputing Cray-style Vectorisation of the Power ISA.
+
+# Checklist for adding an instruction
+
+TODO.  use the commit diffs for these instructions as a guide
+
+* fmvis <https://bugs.libre-soc.org/show_bug.cgi?id=887>
+* avgadd etc. <https://bugs.libre-soc.org/show_bug.cgi?id=863>
+* int min/max <https://bugs.libre-soc.org/show_bug.cgi?id=234#c1>
+* ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745> which included
+  adding a hardware implementation as well