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Merge pull request #6 from sifive/remove-consts-vh
[freedom-sifive.git]
/
fpga
/
u500vc707devkit
/
script
/
prologue.tcl
diff --git
a/fpga/u500vc707devkit/script/prologue.tcl
b/fpga/u500vc707devkit/script/prologue.tcl
index 91fdf974d73fbb101a11a75eced8281f7d1e290b..0fca22835eeb9f5e12c70275096b135898dbb9b7 100644
(file)
--- a/
fpga/u500vc707devkit/script/prologue.tcl
+++ b/
fpga/u500vc707devkit/script/prologue.tcl
@@
-50,15
+50,10
@@
if {[info exists ::env(EXTRA_VSRCS)]} {
#}
set vsrc_top $::env(VSRC_TOP)
#}
set vsrc_top $::env(VSRC_TOP)
-set vsrc_consts $::env(VSRC_CONSTS)
-set_property verilog_define [list \
- "VSRC_CONSTS=${vsrc_consts}" \
- "VSRC_TOP=${vsrc_top}" \
- ] $obj
+set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
add_files -norecurse -fileset $obj $vsrc_top
add_files -norecurse -fileset $obj $vsrc_top
-add_files -norecurse -fileset $obj $vsrc_consts
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1