+#ifdef GCC_INSN_CODES_H
+/* Each reload is recorded with a structure like this. */
+struct reload
+{
+ /* The value to reload from */
+ rtx in;
+ /* Where to store reload-reg afterward if nec (often the same as
+ reload_in) */
+ rtx out;
+
+ /* The class of registers to reload into. */
+ enum reg_class rclass;
+
+ /* The mode this operand should have when reloaded, on input. */
+ enum machine_mode inmode;
+ /* The mode this operand should have when reloaded, on output. */
+ enum machine_mode outmode;
+
+ /* The mode of the reload register. */
+ enum machine_mode mode;
+
+ /* the largest number of registers this reload will require. */
+ unsigned int nregs;
+
+ /* Positive amount to increment or decrement by if
+ reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC.
+ Ignored otherwise (don't assume it is zero). */
+ int inc;
+ /* A reg for which reload_in is the equivalent.
+ If reload_in is a symbol_ref which came from
+ reg_equiv_constant, then this is the pseudo
+ which has that symbol_ref as equivalent. */
+ rtx in_reg;
+ rtx out_reg;
+
+ /* Used in find_reload_regs to record the allocated register. */
+ int regno;
+ /* This is the register to reload into. If it is zero when `find_reloads'
+ returns, you must find a suitable register in the class specified by
+ reload_reg_class, and store here an rtx for that register with mode from
+ reload_inmode or reload_outmode. */
+ rtx reg_rtx;
+ /* The operand number being reloaded. This is used to group related reloads
+ and need not always be equal to the actual operand number in the insn,
+ though it current will be; for in-out operands, it is one of the two
+ operand numbers. */
+ int opnum;
+
+ /* Gives the reload number of a secondary input reload, when needed;
+ otherwise -1. */
+ int secondary_in_reload;
+ /* Gives the reload number of a secondary output reload, when needed;
+ otherwise -1. */
+ int secondary_out_reload;
+ /* If a secondary input reload is required, gives the INSN_CODE that uses the
+ secondary reload as a scratch register, or CODE_FOR_nothing if the
+ secondary reload register is to be an intermediate register. */
+ enum insn_code secondary_in_icode;
+ /* Likewise, for a secondary output reload. */
+ enum insn_code secondary_out_icode;
+
+ /* Classifies reload as needed either for addressing an input reload,
+ addressing an output, for addressing a non-reloaded mem ref, or for
+ unspecified purposes (i.e., more than one of the above). */
+ enum reload_type when_needed;
+
+ /* Nonzero for an optional reload. Optional reloads are ignored unless the
+ value is already sitting in a register. */
+ unsigned int optional:1;
+ /* nonzero if this reload shouldn't be combined with another reload. */
+ unsigned int nocombine:1;
+ /* Nonzero if this is a secondary register for one or more reloads. */
+ unsigned int secondary_p:1;
+ /* Nonzero if this reload must use a register not already allocated to a
+ group. */
+ unsigned int nongroup:1;
+};
+
+extern struct reload rld[MAX_RELOADS];
+extern int n_reloads;
+#endif
+
+/* Target-dependent globals. */
+struct target_reload {
+ /* Nonzero if indirect addressing is supported when the innermost MEM is
+ of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
+ which these are valid is the same as spill_indirect_levels, above. */
+ bool x_indirect_symref_ok;
+
+ /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
+ bool x_double_reg_address_ok;
+
+ /* Nonzero if indirect addressing is supported on the machine; this means
+ that spilling (REG n) does not require reloading it into a register in
+ order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
+ value indicates the level of indirect addressing supported, e.g., two
+ means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
+ a hard register. */
+ bool x_spill_indirect_levels;
+
+ /* True if caller-save has been reinitialized. */
+ bool x_caller_save_initialized_p;
+
+ /* Modes for each hard register that we can save. The smallest mode is wide
+ enough to save the entire contents of the register. When saving the
+ register because it is live we first try to save in multi-register modes.
+ If that is not possible the save is done one register at a time. */
+ enum machine_mode (x_regno_save_mode
+ [FIRST_PSEUDO_REGISTER]
+ [MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1]);
+
+ /* We will only make a register eligible for caller-save if it can be
+ saved in its widest mode with a simple SET insn as long as the memory
+ address is valid. We record the INSN_CODE is those insns here since
+ when we emit them, the addresses might not be valid, so they might not
+ be recognized. */
+ int x_cached_reg_save_code[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
+ int x_cached_reg_restore_code[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
+};