+/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
+ and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
+ implementation of this triggers at "fixup" from the same objfile as
+ "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
+ "__dl_runtime_resolve" directly. An unresolved lazy binding
+ stub will point to _dl_runtime_resolve, which will first call
+ __dl_runtime_resolve, and then pass control to the resolved
+ function. */
+
+static CORE_ADDR
+mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ struct minimal_symbol *resolver;
+
+ resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
+
+ if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
+ return frame_unwind_caller_pc (get_current_frame ());
+
+ return glibc_skip_solib_resolver (gdbarch, pc);
+}
+
+/* Signal trampoline support. There are four supported layouts for a
+ signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
+ n64 rt_sigframe. We handle them all independently; not the most
+ efficient way, but simplest. First, declare all the unwinders. */
+
+static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
+ struct frame_info *this_frame,
+ struct trad_frame_cache *this_cache,
+ CORE_ADDR func);
+
+static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
+ struct frame_info *this_frame,
+ struct trad_frame_cache *this_cache,
+ CORE_ADDR func);
+
+#define MIPS_NR_LINUX 4000
+#define MIPS_NR_N64_LINUX 5000
+#define MIPS_NR_N32_LINUX 6000
+
+#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
+#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
+#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
+#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
+
+#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
+#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
+#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
+#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
+#define MIPS_INST_SYSCALL 0x0000000c
+
+static const struct tramp_frame mips_linux_o32_sigframe = {
+ SIGTRAMP_FRAME,
+ 4,
+ {
+ { MIPS_INST_LI_V0_SIGRETURN, -1 },
+ { MIPS_INST_SYSCALL, -1 },
+ { TRAMP_SENTINEL_INSN, -1 }
+ },
+ mips_linux_o32_sigframe_init
+};
+
+static const struct tramp_frame mips_linux_o32_rt_sigframe = {
+ SIGTRAMP_FRAME,
+ 4,
+ {
+ { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
+ { MIPS_INST_SYSCALL, -1 },
+ { TRAMP_SENTINEL_INSN, -1 } },
+ mips_linux_o32_sigframe_init
+};
+
+static const struct tramp_frame mips_linux_n32_rt_sigframe = {
+ SIGTRAMP_FRAME,
+ 4,
+ {
+ { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
+ { MIPS_INST_SYSCALL, -1 },
+ { TRAMP_SENTINEL_INSN, -1 }
+ },
+ mips_linux_n32n64_sigframe_init
+};
+
+static const struct tramp_frame mips_linux_n64_rt_sigframe = {
+ SIGTRAMP_FRAME,
+ 4,
+ {
+ { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
+ { MIPS_INST_SYSCALL, -1 },
+ { TRAMP_SENTINEL_INSN, -1 }
+ },
+ mips_linux_n32n64_sigframe_init
+};
+
+/* *INDENT-OFF* */
+/* The unwinder for o32 signal frames. The legacy structures look
+ like this:
+
+ struct sigframe {
+ u32 sf_ass[4]; [argument save space for o32]
+ u32 sf_code[2]; [signal trampoline or fill]
+ struct sigcontext sf_sc;
+ sigset_t sf_mask;
+ };
+
+ struct sigcontext {
+ unsigned int sc_regmask; [Unused]
+ unsigned int sc_status;
+ unsigned long long sc_pc;
+ unsigned long long sc_regs[32];
+ unsigned long long sc_fpregs[32];
+ unsigned int sc_ownedfp;
+ unsigned int sc_fpc_csr;
+ unsigned int sc_fpc_eir; [Unused]
+ unsigned int sc_used_math;
+ unsigned int sc_ssflags; [Unused]
+ [Alignment hole of four bytes]
+ unsigned long long sc_mdhi;
+ unsigned long long sc_mdlo;
+
+ unsigned int sc_cause; [Unused]
+ unsigned int sc_badvaddr; [Unused]
+
+ unsigned long sc_sigset[4]; [kernel's sigset_t]
+ };
+
+ The RT signal frames look like this:
+
+ struct rt_sigframe {
+ u32 rs_ass[4]; [argument save space for o32]
+ u32 rs_code[2] [signal trampoline or fill]
+ struct siginfo rs_info;
+ struct ucontext rs_uc;
+ };
+
+ struct ucontext {
+ unsigned long uc_flags;
+ struct ucontext *uc_link;
+ stack_t uc_stack;
+ [Alignment hole of four bytes]
+ struct sigcontext uc_mcontext;
+ sigset_t uc_sigmask;
+ }; */
+/* *INDENT-ON* */
+
+#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
+
+#define RTSIGFRAME_SIGINFO_SIZE 128
+#define STACK_T_SIZE (3 * 4)
+#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
+#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ + RTSIGFRAME_SIGINFO_SIZE \
+ + UCONTEXT_SIGCONTEXT_OFFSET)
+
+#define SIGCONTEXT_PC (1 * 8)
+#define SIGCONTEXT_REGS (2 * 8)
+#define SIGCONTEXT_FPREGS (34 * 8)
+#define SIGCONTEXT_FPCSR (66 * 8 + 4)
+#define SIGCONTEXT_HI (69 * 8)
+#define SIGCONTEXT_LO (70 * 8)
+#define SIGCONTEXT_CAUSE (71 * 8 + 0)
+#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
+
+#define SIGCONTEXT_REG_SIZE 8
+
+static void
+mips_linux_o32_sigframe_init (const struct tramp_frame *self,
+ struct frame_info *this_frame,
+ struct trad_frame_cache *this_cache,
+ CORE_ADDR func)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ int ireg, reg_position;
+ CORE_ADDR frame_sp = get_frame_sp (this_frame);
+ CORE_ADDR sigcontext_base;
+ const struct mips_regnum *regs = mips_regnum (gdbarch);
+ CORE_ADDR regs_base;
+
+ if (self == &mips_linux_o32_sigframe)
+ sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
+ else
+ sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
+
+ /* I'm not proud of this hack. Eventually we will have the
+ infrastructure to indicate the size of saved registers on a
+ per-frame basis, but right now we don't; the kernel saves eight
+ bytes but we only want four. Use regs_base to access any
+ 64-bit fields. */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ regs_base = sigcontext_base + 4;
+ else
+ regs_base = sigcontext_base;
+
+ if (mips_linux_restart_reg_p (gdbarch))
+ trad_frame_set_reg_addr (this_cache,
+ (MIPS_RESTART_REGNUM
+ + gdbarch_num_regs (gdbarch)),
+ regs_base + SIGCONTEXT_REGS);
+
+ for (ireg = 1; ireg < 32; ireg++)
+ trad_frame_set_reg_addr (this_cache,
+ ireg + MIPS_ZERO_REGNUM
+ + gdbarch_num_regs (gdbarch),
+ regs_base + SIGCONTEXT_REGS
+ + ireg * SIGCONTEXT_REG_SIZE);
+
+ /* The way that floating point registers are saved, unfortunately,
+ depends on the architecture the kernel is built for. For the r3000 and
+ tx39, four bytes of each register are at the beginning of each of the
+ 32 eight byte slots. For everything else, the registers are saved
+ using double precision; only the even-numbered slots are initialized,
+ and the high bits are the odd-numbered register. Assume the latter
+ layout, since we can't tell, and it's much more common. Which bits are
+ the "high" bits depends on endianness. */
+ for (ireg = 0; ireg < 32; ireg++)
+ if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
+ trad_frame_set_reg_addr (this_cache,
+ ireg + regs->fp0 +
+ gdbarch_num_regs (gdbarch),
+ sigcontext_base + SIGCONTEXT_FPREGS + 4
+ + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
+ else
+ trad_frame_set_reg_addr (this_cache,
+ ireg + regs->fp0
+ + gdbarch_num_regs (gdbarch),
+ sigcontext_base + SIGCONTEXT_FPREGS
+ + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
+
+ trad_frame_set_reg_addr (this_cache,
+ regs->pc + gdbarch_num_regs (gdbarch),
+ regs_base + SIGCONTEXT_PC);
+
+ trad_frame_set_reg_addr (this_cache,
+ regs->fp_control_status
+ + gdbarch_num_regs (gdbarch),
+ sigcontext_base + SIGCONTEXT_FPCSR);
+ trad_frame_set_reg_addr (this_cache,
+ regs->hi + gdbarch_num_regs (gdbarch),
+ regs_base + SIGCONTEXT_HI);
+ trad_frame_set_reg_addr (this_cache,
+ regs->lo + gdbarch_num_regs (gdbarch),
+ regs_base + SIGCONTEXT_LO);
+ trad_frame_set_reg_addr (this_cache,
+ regs->cause + gdbarch_num_regs (gdbarch),
+ sigcontext_base + SIGCONTEXT_CAUSE);
+ trad_frame_set_reg_addr (this_cache,
+ regs->badvaddr + gdbarch_num_regs (gdbarch),
+ sigcontext_base + SIGCONTEXT_BADVADDR);
+
+ /* Choice of the bottom of the sigframe is somewhat arbitrary. */
+ trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
+}
+
+/* *INDENT-OFF* */
+/* For N32/N64 things look different. There is no non-rt signal frame.
+
+ struct rt_sigframe_n32 {
+ u32 rs_ass[4]; [ argument save space for o32 ]
+ u32 rs_code[2]; [ signal trampoline or fill ]
+ struct siginfo rs_info;
+ struct ucontextn32 rs_uc;
+ };
+
+ struct ucontextn32 {
+ u32 uc_flags;
+ s32 uc_link;
+ stack32_t uc_stack;
+ struct sigcontext uc_mcontext;
+ sigset_t uc_sigmask; [ mask last for extensibility ]
+ };
+
+ struct rt_sigframe {
+ u32 rs_ass[4]; [ argument save space for o32 ]
+ u32 rs_code[2]; [ signal trampoline ]
+ struct siginfo rs_info;
+ struct ucontext rs_uc;
+ };
+
+ struct ucontext {
+ unsigned long uc_flags;
+ struct ucontext *uc_link;
+ stack_t uc_stack;
+ struct sigcontext uc_mcontext;
+ sigset_t uc_sigmask; [ mask last for extensibility ]
+ };
+
+ And the sigcontext is different (this is for both n32 and n64):
+
+ struct sigcontext {
+ unsigned long long sc_regs[32];
+ unsigned long long sc_fpregs[32];
+ unsigned long long sc_mdhi;
+ unsigned long long sc_hi1;
+ unsigned long long sc_hi2;
+ unsigned long long sc_hi3;
+ unsigned long long sc_mdlo;
+ unsigned long long sc_lo1;
+ unsigned long long sc_lo2;
+ unsigned long long sc_lo3;
+ unsigned long long sc_pc;
+ unsigned int sc_fpc_csr;
+ unsigned int sc_used_math;
+ unsigned int sc_dsp;
+ unsigned int sc_reserved;
+ };
+
+ That is the post-2.6.12 definition of the 64-bit sigcontext; before
+ then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
+ included too. */
+/* *INDENT-ON* */
+
+#define N32_STACK_T_SIZE STACK_T_SIZE
+#define N64_STACK_T_SIZE (2 * 8 + 4)
+#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
+#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
+#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ + RTSIGFRAME_SIGINFO_SIZE \
+ + N32_UCONTEXT_SIGCONTEXT_OFFSET)
+#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
+ + RTSIGFRAME_SIGINFO_SIZE \
+ + N64_UCONTEXT_SIGCONTEXT_OFFSET)
+
+#define N64_SIGCONTEXT_REGS (0 * 8)
+#define N64_SIGCONTEXT_FPREGS (32 * 8)
+#define N64_SIGCONTEXT_HI (64 * 8)
+#define N64_SIGCONTEXT_LO (68 * 8)
+#define N64_SIGCONTEXT_PC (72 * 8)
+#define N64_SIGCONTEXT_FPCSR (73 * 8)
+
+#define N64_SIGCONTEXT_REG_SIZE 8
+
+static void
+mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
+ struct frame_info *this_frame,
+ struct trad_frame_cache *this_cache,
+ CORE_ADDR func)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ int ireg, reg_position;
+ CORE_ADDR frame_sp = get_frame_sp (this_frame);
+ CORE_ADDR sigcontext_base;
+ const struct mips_regnum *regs = mips_regnum (gdbarch);
+
+ if (self == &mips_linux_n32_rt_sigframe)
+ sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
+ else
+ sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
+
+ if (mips_linux_restart_reg_p (gdbarch))
+ trad_frame_set_reg_addr (this_cache,
+ (MIPS_RESTART_REGNUM
+ + gdbarch_num_regs (gdbarch)),
+ sigcontext_base + N64_SIGCONTEXT_REGS);
+
+ for (ireg = 1; ireg < 32; ireg++)
+ trad_frame_set_reg_addr (this_cache,
+ ireg + MIPS_ZERO_REGNUM
+ + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_REGS
+ + ireg * N64_SIGCONTEXT_REG_SIZE);
+
+ for (ireg = 0; ireg < 32; ireg++)
+ trad_frame_set_reg_addr (this_cache,
+ ireg + regs->fp0
+ + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_FPREGS
+ + ireg * N64_SIGCONTEXT_REG_SIZE);
+
+ trad_frame_set_reg_addr (this_cache,
+ regs->pc + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_PC);
+
+ trad_frame_set_reg_addr (this_cache,
+ regs->fp_control_status
+ + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_FPCSR);
+ trad_frame_set_reg_addr (this_cache,
+ regs->hi + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_HI);
+ trad_frame_set_reg_addr (this_cache,
+ regs->lo + gdbarch_num_regs (gdbarch),
+ sigcontext_base + N64_SIGCONTEXT_LO);
+
+ /* Choice of the bottom of the sigframe is somewhat arbitrary. */
+ trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
+}
+
+static void
+mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), pc);
+
+ /* Clear the syscall restart flag. */
+ if (mips_linux_restart_reg_p (gdbarch))
+ regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
+}
+
+/* Return 1 if MIPS_RESTART_REGNUM is usable. */
+
+int
+mips_linux_restart_reg_p (struct gdbarch *gdbarch)
+{
+ /* If we do not have a target description with registers, then
+ MIPS_RESTART_REGNUM will not be included in the register set. */
+ if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
+ return 0;
+
+ /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
+ either be GPR-sized or missing. */
+ return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
+}
+
+/* When FRAME is at a syscall instruction, return the PC of the next
+ instruction to be executed. */
+
+static CORE_ADDR
+mips_linux_syscall_next_pc (struct frame_info *frame)
+{
+ CORE_ADDR pc = get_frame_pc (frame);
+ ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
+
+ /* If we are about to make a sigreturn syscall, use the unwinder to
+ decode the signal frame. */
+ if (v0 == MIPS_NR_sigreturn
+ || v0 == MIPS_NR_rt_sigreturn
+ || v0 == MIPS_NR_N64_rt_sigreturn
+ || v0 == MIPS_NR_N32_rt_sigreturn)
+ return frame_unwind_caller_pc (get_current_frame ());
+
+ return pc + 4;
+}
+
+/* Initialize one of the GNU/Linux OS ABIs. */
+
+static void
+mips_linux_init_abi (struct gdbarch_info info,
+ struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ enum mips_abi abi = mips_abi (gdbarch);
+ struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
+
+ switch (abi)
+ {
+ case MIPS_ABI_O32:
+ set_gdbarch_get_longjmp_target (gdbarch,
+ mips_linux_get_longjmp_target);
+ set_solib_svr4_fetch_link_map_offsets
+ (gdbarch, svr4_ilp32_fetch_link_map_offsets);
+ tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
+ tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
+ break;
+ case MIPS_ABI_N32:
+ set_gdbarch_get_longjmp_target (gdbarch,
+ mips_linux_get_longjmp_target);
+ set_solib_svr4_fetch_link_map_offsets
+ (gdbarch, svr4_ilp32_fetch_link_map_offsets);
+ set_gdbarch_long_double_bit (gdbarch, 128);
+ /* These floatformats should probably be renamed. MIPS uses
+ the same 128-bit IEEE floating point format that IA-64 uses,
+ except that the quiet/signalling NaN bit is reversed (GDB
+ does not distinguish between quiet and signalling NaNs). */
+ set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
+ tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
+ break;
+ case MIPS_ABI_N64:
+ set_gdbarch_get_longjmp_target (gdbarch,
+ mips64_linux_get_longjmp_target);
+ set_solib_svr4_fetch_link_map_offsets
+ (gdbarch, svr4_lp64_fetch_link_map_offsets);
+ set_gdbarch_long_double_bit (gdbarch, 128);
+ /* These floatformats should probably be renamed. MIPS uses
+ the same 128-bit IEEE floating point format that IA-64 uses,
+ except that the quiet/signalling NaN bit is reversed (GDB
+ does not distinguish between quiet and signalling NaNs). */
+ set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
+ tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
+ break;
+ default:
+ break;
+ }
+
+ set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
+
+ set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
+
+ /* Enable TLS support. */
+ set_gdbarch_fetch_tls_load_module_address (gdbarch,
+ svr4_fetch_objfile_link_map);
+
+ /* Initialize this lazily, to avoid an initialization order
+ dependency on solib-svr4.c's _initialize routine. */
+ if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
+ {
+ mips_svr4_so_ops = svr4_so_ops;
+ mips_svr4_so_ops.in_dynsym_resolve_code
+ = mips_linux_in_dynsym_resolve_code;
+ }
+ set_solib_ops (gdbarch, &mips_svr4_so_ops);
+
+ set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
+
+ set_gdbarch_core_read_description (gdbarch,
+ mips_linux_core_read_description);
+
+ tdep->syscall_next_pc = mips_linux_syscall_next_pc;
+
+ if (tdesc_data)
+ {
+ const struct tdesc_feature *feature;
+
+ /* If we have target-described registers, then we can safely
+ reserve a number for MIPS_RESTART_REGNUM (whether it is
+ described or not). */
+ gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
+ set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
+
+ /* If it's present, then assign it to the reserved number. */
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.mips.linux");
+ if (feature != NULL)
+ tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
+ "restart");
+ }
+}
+
+/* Provide a prototype to silence -Wmissing-prototypes. */
+extern initialize_file_ftype _initialize_mips_linux_tdep;
+