+static int
+or1k_delay_slot_p (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ const CGEN_INSN *insn;
+ CGEN_FIELDS tmp_fields;
+ or1k_gdbarch_tdep *tdep = gdbarch_tdep<or1k_gdbarch_tdep> (gdbarch);
+
+ insn = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc,
+ NULL,
+ or1k_fetch_instruction (gdbarch, pc),
+ NULL, 32, &tmp_fields, 0);
+
+ /* NULL here would mean the last instruction was not understood by cgen.
+ This should not usually happen, but if does its not a delay slot. */
+ if (insn == NULL)
+ return 0;
+
+ /* TODO: we should add a delay slot flag to the CGEN_INSN and remove
+ this hard coded test. */
+ return ((CGEN_INSN_NUM (insn) == OR1K_INSN_L_J)
+ || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JAL)
+ || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JR)
+ || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JALR)
+ || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BNF)
+ || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BF));
+}
+