- processor. */
-
-/* UISA register names common across all architectures, including POWER. */
-
-#define COMMON_UISA_REG_NAMES \
- /* 0 */ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- /* 8 */ "r8", "r9", "r10","r11","r12","r13","r14","r15", \
- /* 16 */ "r16","r17","r18","r19","r20","r21","r22","r23", \
- /* 24 */ "r24","r25","r26","r27","r28","r29","r30","r31", \
- /* 32 */ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
- /* 40 */ "f8", "f9", "f10","f11","f12","f13","f14","f15", \
- /* 48 */ "f16","f17","f18","f19","f20","f21","f22","f23", \
- /* 56 */ "f24","f25","f26","f27","f28","f29","f30","f31", \
- /* 64 */ "pc", "ps"
-
-/* UISA-level SPR names for PowerPC. */
-#define PPC_UISA_SPR_NAMES \
- /* 66 */ "cr", "lr", "ctr", "xer", ""
-
-/* Segment register names, for PowerPC. */
-#define PPC_SEGMENT_REG_NAMES \
- /* 71 */ "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", \
- /* 79 */ "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
-
-/* OEA SPR names for 32-bit PowerPC implementations.
- The blank space is for "asr", which is only present on 64-bit
- implementations. */
-#define PPC_32_OEA_SPR_NAMES \
- /* 87 */ "pvr", \
- /* 88 */ "ibat0u", "ibat0l", "ibat1u", "ibat1l", \
- /* 92 */ "ibat2u", "ibat2l", "ibat3u", "ibat3l", \
- /* 96 */ "dbat0u", "dbat0l", "dbat1u", "dbat1l", \
- /* 100 */ "dbat2u", "dbat2l", "dbat3u", "dbat3l", \
- /* 104 */ "sdr1", "", "dar", "dsisr", "sprg0", "sprg1", "sprg2", "sprg3",\
- /* 112 */ "srr0", "srr1", "tbl", "tbu", "dec", "dabr", "ear"
-
-/* For the RS6000, we only cover user-level SPR's. */
-char *register_names_rs6000[] =
+ processor. */
+
+/* Convenience macros for populating register arrays. */
+
+/* Within another macro, convert S to a string. */
+
+#define STR(s) #s
+
+/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
+ and 64 bits on 64-bit systems. */
+#define R(name) { STR(name), 4, 8, 0 }
+
+/* Return a struct reg defining register NAME that's 32 bits on all
+ systems. */
+#define R4(name) { STR(name), 4, 4, 0 }
+
+/* Return a struct reg defining register NAME that's 64 bits on all
+ systems. */
+#define R8(name) { STR(name), 8, 8, 0 }
+
+/* Return a struct reg defining floating-point register NAME. */
+#define F(name) { STR(name), 8, 8, 1 }
+
+/* Return a struct reg defining register NAME that's 32 bits on 32-bit
+ systems and that doesn't exist on 64-bit systems. */
+#define R32(name) { STR(name), 4, 0, 0 }
+
+/* Return a struct reg defining register NAME that's 64 bits on 64-bit
+ systems and that doesn't exist on 32-bit systems. */
+#define R64(name) { STR(name), 0, 8, 0 }
+
+/* Return a struct reg placeholder for a register that doesn't exist. */
+#define R0 { 0, 0, 0, 0 }
+
+/* UISA registers common across all architectures, including POWER. */
+
+#define COMMON_UISA_REGS \
+ /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
+ /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
+ /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
+ /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
+ /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
+ /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
+ /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
+ /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
+ /* 64 */ R(pc), R(ps)
+
+/* UISA-level SPRs for PowerPC. */
+#define PPC_UISA_SPRS \
+ /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
+
+/* Segment registers, for PowerPC. */
+#define PPC_SEGMENT_REGS \
+ /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
+ /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
+ /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
+ /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
+
+/* OEA SPRs for PowerPC. */
+#define PPC_OEA_SPRS \
+ /* 87 */ R4(pvr), \
+ /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
+ /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
+ /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
+ /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
+ /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
+ /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
+ /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
+ /* 116 */ R4(dec), R(dabr), R4(ear)
+
+/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
+ user-level SPR's. */
+static const struct reg registers_power[] =