- p_DQS_LI_DEL_ADJ="MINUS",
- p_DQS_LI_DEL_VAL=1,
- p_DQS_LO_DEL_ADJ="MINUS",
- p_DQS_LO_DEL_VAL=4,
-
- # Delay
- i_DYNDELAY0=0,
- i_DYNDELAY1=0,
- i_DYNDELAY2=0,
- i_DYNDELAY3=0,
- i_DYNDELAY4=0,
- i_DYNDELAY5=0,
- i_DYNDELAY6=0,
- i_DYNDELAY7=0,
-
- # Clocks / Reset
- i_SCLK=ClockSignal("sync"),
- i_ECLK=ClockSignal("sync2x"),
- i_RST=ResetSignal("dramsync"),
- i_DDRDEL=init.delay,
- i_PAUSE=init.pause | self._dly_sel.w_data[i],
-
- # Control
- # Assert LOADNs to use DDRDEL control
- i_RDLOADN=0,
- i_RDMOVE=0,
- i_RDDIRECTION=1,
- i_WRLOADN=0,
- i_WRMOVE=0,
- i_WRDIRECTION=1,
-
- # Reads (generate shifted DQS clock for reads)
- i_READ0=1,
- i_READ1=1,
- i_READCLKSEL0=rdly[0],
- i_READCLKSEL1=rdly[1],
- i_READCLKSEL2=rdly[2],
- i_DQSI=dqs_i,
- o_DQSR90=dqsr90,
- o_RDPNTR0=rdpntr[0],
- o_RDPNTR1=rdpntr[1],
- o_RDPNTR2=rdpntr[2],
- o_WRPNTR0=wrpntr[0],
- o_WRPNTR1=wrpntr[1],
- o_WRPNTR2=wrpntr[2],
- o_DATAVALID=self.datavalid[i],
- o_BURSTDET=burstdet,
-
- # Writes (generate shifted ECLK clock for writes)
- o_DQSW270=dqsw270,
- o_DQSW=dqsw)
- burstdet_d = Signal()
- m.d.sync += burstdet_d.eq(burstdet)
- with m.If(self._burstdet_clr.w_stb):
- m.d.sync += self._burstdet_seen.r_data[i].eq(0)
- with m.If(burstdet & ~burstdet_d):
- m.d.sync += self._burstdet_seen.r_data[i].eq(1)
+ p_DQS_LI_DEL_ADJ="MINUS",
+ p_DQS_LI_DEL_VAL=1,
+ p_DQS_LO_DEL_ADJ="MINUS",
+ p_DQS_LO_DEL_VAL=4,
+
+ # Delay
+ i_DYNDELAY0=0,
+ i_DYNDELAY1=0,
+ i_DYNDELAY2=0,
+ i_DYNDELAY3=0,
+ i_DYNDELAY4=0,
+ i_DYNDELAY5=0,
+ i_DYNDELAY6=0,
+ i_DYNDELAY7=0,
+
+ # Clocks / Reset
+ i_SCLK=ClockSignal("sync"),
+ i_ECLK=ClockSignal("sync2x"),
+ i_RST=ResetSignal("dramsync"),
+ i_DDRDEL=init.delay,
+ i_PAUSE=init.pause | self.rdly[i].w_stb,
+
+ # Control
+ # Assert LOADNs to use DDRDEL control
+ i_RDLOADN=0,
+ i_RDMOVE=0,
+ i_RDDIRECTION=1,
+ i_WRLOADN=0,
+ i_WRMOVE=0,
+ i_WRDIRECTION=1,
+
+ # Reads (generate shifted DQS clock for reads)
+ i_READ0=dqs_re,
+ i_READ1=dqs_re,
+ i_READCLKSEL0=self.rdly[i].w_data[0],
+ i_READCLKSEL1=self.rdly[i].w_data[1],
+ i_READCLKSEL2=self.rdly[i].w_data[2],
+ i_DQSI=dqs_i,
+ o_DQSR90=dqsr90,
+ o_RDPNTR0=rdpntr[0],
+ o_RDPNTR1=rdpntr[1],
+ o_RDPNTR2=rdpntr[2],
+ o_WRPNTR0=wrpntr[0],
+ o_WRPNTR1=wrpntr[1],
+ o_WRPNTR2=wrpntr[2],
+ o_DATAVALID=self.datavalid[i],
+ o_BURSTDET=burstdet,
+
+ # Writes (generate shifted ECLK clock for writes)
+ o_DQSW270=dqsw270,
+ o_DQSW=dqsw)
+
+ with m.If(burstdet):
+ m.d.sync += burstdet_reg[i].eq(1)