- for i in range(addressbits):
- m.submodules += Instance("ODDRX2F",
- i_RST=ResetSignal("sync2x"),
- i_ECLK=ClockSignal("sync2x"),
- i_SCLK=ClockSignal(),
- i_D0=dfi.phases[0].address[i],
- i_D1=dfi.phases[0].address[i],
- i_D2=dfi.phases[1].address[i],
- i_D3=dfi.phases[1].address[i],
- o_Q=self.pads.a.o[i]
- )
- for i in range(bankbits):
- m.submodules += Instance("ODDRX2F",
- i_RST=ResetSignal("sync2x"),
- i_ECLK=ClockSignal("sync2x"),
- i_SCLK=ClockSignal(),
- i_D0=dfi.phases[0].bank[i],
- i_D1=dfi.phases[0].bank[i],
- i_D2=dfi.phases[1].bank[i],
- i_D3=dfi.phases[1].bank[i],
- o_Q=self.pads.ba.o[i]
- )
- controls = ["ras_n", "cas_n", "we_n", "cke", "odt"]
- if hasattr(self.pads, "reset_n"):
- controls.append("reset_n")
- if hasattr(self.pads, "cs_n"):
- controls.append("cs_n")
+ m.d.comb += [
+ self.pads.a.o_clk.eq(ClockSignal("dramsync")),
+ self.pads.a.o_fclk.eq(ClockSignal("sync2x")),
+ self.pads.ba.o_clk.eq(ClockSignal("dramsync")),
+ self.pads.ba.o_fclk.eq(ClockSignal("sync2x")),
+ ]
+ for i in range(len(self.pads.a.o0)):
+ m.d.comb += [
+ self.pads.a.o0[i].eq(dfi.phases[0].address[i]),
+ self.pads.a.o1[i].eq(dfi.phases[0].address[i]),
+ self.pads.a.o2[i].eq(dfi.phases[1].address[i]),
+ self.pads.a.o3[i].eq(dfi.phases[1].address[i]),
+ ]
+ for i in range(len(self.pads.ba.o0)):
+ m.d.comb += [
+ self.pads.ba.o0[i].eq(dfi.phases[0].bank[i]),
+ self.pads.ba.o1[i].eq(dfi.phases[0].bank[i]),
+ self.pads.ba.o2[i].eq(dfi.phases[1].bank[i]),
+ self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]),
+ ]
+
+ # Control pins
+ controls = ["ras", "cas", "we", "clk_en", "odt"]
+ if hasattr(self.pads, "reset"):
+ controls.append("reset")
+ if hasattr(self.pads, "cs"):
+ controls.append("cs")